Gurindar S. Sohi

Patents

Each patent title and patent number links directly to that specific Google Patents record.

• Computer architecture using program counter indexed data address translation
  G. S. Sohi and S. Murthy
  U.S. Patent 12,517,838 B2. Issued January 6, 2026.
• Computer system with instruction pre-sending
  G. S. Sohi and S. Murthy
  U.S. Patent 12,386,533. Issued August 12, 2025.
• Computer architecture for speculative parallel execution
  G. Gupta and G. S. Sohi
  U.S. Patent 10,209,997. Issued February 19, 2019.
• Precise-Restartable Parallel Execution of Programs
  G. Gupta and G. S. Sohi
  U.S. Patent 10,185,569. Issued January 22, 2019.
• Cache accessed using virtual addresses
  G. S. Sohi and H. Yoon
  U.S. Patent 10,089,240. Issued October 2, 2018.
• System and method for selectively delaying execution of an operation based on a search for uncompleted predicate operations in processor-associated queues
  G. Gupta, G. S. Sohi, and S. Sridharan
  U.S. Patent 9,830,157. Issued November 28, 2017.
• System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens
  G. Gupta, G. S. Sohi, and S. Sridharan
  U.S. Patent 9,652,301. Issued May 16, 2017.
• Computer cache system providing multi-line invalidation messages
  G. S. Sohi and H. Yoon
  U.S. Patent 9,223,717. Issued December 29, 2015.
• Computer system and method for runtime control of parallelism in program execution
  S. Sridharan and G. S. Sohi
  U.S. Patent 9,223,674. Issued December 29, 2015.
• System and method for controlling excessive parallelism in multiprocessor systems
  G. S. Sohi, S. Sridharan, and G. Gupta
  U.S. Patent 8,843,932. Issued September 24, 2014.
• Assigning different serialization identifier to operations on different data set for execution in respective processor in multi-processor system
  M. D. Allen and G. S. Sohi
  U.S. Patent 8,417,919. Issued April 9, 2013.
• Over-provisioned Multicore Processor
  K. Chakraborty, P. M. Wells, and G. S. Sohi
  U.S. Patent 7,962,774. Issued June 14, 2011.
• Data Flow Execution of Methods in a Sequential Program
  S. Balakrishnan and G. S. Sohi
  U.S. Patent 7,779,230. Issued August 17, 2010.
• Method and apparatus for parallel execution of computer software using a distilled program
  C. B. Zilles and G. S. Sohi
  U.S. Patent 6,944,754. Issued September 13, 2005.
• Electronic processor providing direct data transfer between linked data consuming instructions
  A. I. Moshovos and G. S. Sohi
  U.S. Patent 6,658,554. Issued December 2, 2003.
• Data Cache Fast Address Calculation System and Method
  T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi
  U.S. Patent 5,860,151. Issued January 12, 1999.
• Computer with Dynamic Instruction Reuse
  A. Sodani and G. S. Sohi
  U.S. Patent 5,845,103. Issued December 1, 1998.
• Table Based Data Speculation Circuit for Parallel Processing Computer
  A. I. Moshovos, S. E. Breach, T. N. Vijaykumar, and G. S. Sohi
  U.S. Patent 5,781,752. Issued July 14, 1998.