Gurindar S. Sohi

Publications

Recent Work

• Reducing LLM Inference Memory Bandwidth via Frequent Exponent Value Encoding,"
  M. Michalec, S. Tannu, and G. S. Sohi,
  2026
• Instruction Block Movement with Coupled High-Level Program Sequencing
  Shyam Murthy and G. S. Sohi
  2024
• A Non-Traditional Approach to Assisting Data Address Translation
  Shyam Murthy and G. S. Sohi
  2024
• Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses
  Vanshika Baoni, Adarsh Mittal, and G. S. Sohi
  2021

Books and Book Chapters

• J. Chang, E. Herrero, R. Canal, G. S. Sohi, “Cooperative Caching for Chip Multiprocessors, in Cooperative Networking, John Wiley and Sons, 2011.
• G. S. Sohi and T. N. Vijaykumar, “Speculative Multithreaded Processors,” in Multicore Processors and Systems, Springer, 2009.
• G. S. Sohi, 25 Years of the International Symposium on Computer Architecture - Selected Papers, ACM Press, 1998. ISBN: 1-58113-058-9.
• Mark D. Hill, Norman P. Jouppi and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, San Francisco, CA, 2000. ISBN: 1-55860-539-8.
• G. S. Sohi, “Retrospective on Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors,” in 25 Years of the International Symposium on Computer Architecture - Selected Papers, ACM Press, 1998.
• G. S. Sohi, “Retrospective on Multiscalar Processors,” in 25 Years of the International Symposium on Computer Architecture - Selected Papers, ACM Press, 1998.
• D. Burger, J. R. Goodman and G. S. Sohi, “Memory Systems,” in The Handbook of Computer Science and Engineering, CRC Press, 1997, pp. 447-461.
• J. R. Goodman and G. S. Sohi, “Memory Systems,” in The Handbook of Electrical Engineering, CRC Press, 1993, pp. 1927-1937.

Journals

• M. Michalec, S. Tannu, and G. S. Sohi, "Reducing LLM Inference Memory Bandwidth via Frequent Exponent Value Encoding," IEEE Computer Architecture Letters, vol. 25, no. 1, pp. 85-88, 2026.
• K. Chakraborty, P. Wells, G. S. Sohi, “Supporting Overcommitted Virtual Machines Through Hardware Spin Detection," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 2, Feb. 2012, pp. 353-366.
• A. L. Holloway, G. S. Sohi, “Characterization of Problem Stores,” Computer Architecture Letters, vol. 4, No. 1, March 2005, pp. 14-17.
• J. Huh, D. Burger, J. Chang, G. S. Sohi, “Speculative Incoherent Cache Protocols,” IEEE Micro, vol. 25, No. 1, Nov/Dec 2004, pp. 104-109.
• A. Moshovos and G. S. Sohi, “Reducing Memory Latency via Read-after-Read Memory Dependence Prediction,” IEEE Transactions on Computers, vol. 51, No. 3, March 2002, pp. 313-326.
• T. N. Vijaykumar, S. Gopal, J. E. Smith and G. S. Sohi, “Speculative Versioning Cache,” IEEE Transactions on Parallel and Distributed Systems, vol. 12, no. 12, December 2001.
• A. Moshovos and G. S. Sohi, “Micro-Architectural Innovations: Boosting Processor Performance Beyond Technology Scaling,” invited paper in Proceedings of the IEEE, vol. 89, no. 11, November 2001.
• A. Roth and G. S. Sohi, “Squash Reuse via a Simplified Implementation of Register Integration,” invited paper in The Journal of Instruction-Level Parallelism, vol. 3, October 2001.
• G. S. Sohi and A. Roth, “Speculative Multithreaded Processors,” IEEE Computer, vol. 34, no. 4, April 2001.
• A. Moshovos and G. S. Sohi, “Memory Dependence Prediction in Multimedia Applications,” invited paper in Journal of Instruction Level Parallel Processing, May 2000.
• A. Moshovos and G. S. Sohi, “Speculative Memory Cloaking and Bypassing,” in International Journal of Parallel Programming, October 1999.
• T. N. Vijaykumar and G. S. Sohi, “Task Selection for the Multiscalar Architecture,” Journal of Parallel and Distributed Computing (JPDC), pages 132-158, vol. 58, No.2, August 1999, pp. 132-158.
• M. Franklin and G. S. Sohi, “ARB: A Hardware Mechanism for Dynamic Memory Disambiguation,” IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
• J. E. Smith and G. S. Sohi, “The Microarchitecture of Superscalar Processors,” invited paper in Proceedings of the IEEE, December 1995.
• A. R. Lebeck and G. S. Sohi, “Request Combining in Multiprocessors with Arbitrary Interconnects,” IEEE Transactions on Parallel and Distributed Systems, vol. 5, No. 11, November 1994, pp. 1140-1155.
• G. S. Sohi, “High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study,” IEEE Transactions on Computers, vol. 42, No. 1, January 1993, pp. 34-44.
• M.-C. Chiang and G. S. Sohi, “Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment,” IEEE Transactions on Computers, vol. 41, No. 3, March 1992, pp. 297-317.
• S. L. Scott and G. S. Sohi, “The Use of Feedback in Multiprocessors and its Application to Tree Saturation Control,” IEEE Transactions on Parallel and Distributed Systems, vol. 1, No. 4, October 1990, pp. 385-398.
• D. V. James, A. T. Laundrie, S. Gjessing and G. S. Sohi, “SCI (Scalable Coherent Interface) Cache Coherence,” IEEE Computer, vol. 23, No. 6, June 1990, pp. 74-77. Special Issue on Cache Architectures in Tightly Coupled Multiprocessors.
• G. S. Sohi and W.-C. Hsu, “The Use of Intermediate Memories for Low-Latency Memory Access in Supercomputer Scalar Units,” The Journal of Supercomputing, vol. 4, 1990, pp. 5-21. Special Issue on the best papers from Supercomputing ’88.
• G. S. Sohi, “Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers,” IEEE Transactions on Computers, vol. 39, No. 3, March 1990, pp. 349-359.
• K. Cheung, G. S. Sohi, K. Saluja and D. Pradhan, “Design and Analysis of a Gracefully-Degrading Interleaved Memory System,” IEEE Transactions on Computers, vol. 39, No. 1, January 1990, pp. 63-71.
• M. K. Vernon, R. Jog and G. S. Sohi, “Performance Analysis of Hierarchical Cache-Coherent Multiprocessors,” Performance Evaluation, vol. 9, August 1989, pp. 287-302. Award paper from IFIP WG7.3 Int. Seminar on Performance of Distributed and Parallel Systems, Kyoto, Japan, December 1988.
• G. S. Sohi, “Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors,” IEEE Transactions on Computers, vol. 38, No. 4, April 1989, pp. 484-492. Special Section on High-Yield VLSI Systems.

Reviewed Conferences

• Vanshika Baoni, Adarsh Mittal, and G. S. Sohi, “Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses,” 54th Annual International Symposium on Microarchitecture (MICRO-54), October 2021.
• H. Yoon, J. Lowe-Power and G. S. Sohi, “Filtering Translation Bandwidth with Virtual Caching,” 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), Williamsburg, Virginia, March 2018.
• Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, G. S. Sohi, “ATM: Approximate Task Memoization in the Runtime System,” 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS), Orlando, Florida, May 2017.
• H. Yoon and G. S. Sohi, “Revisiting virtual L1 caches: A practical design using dynamic synonym remapping,” 22nd International Symposium on High-Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016
• S. Sridharan, G. Gupta, G. S. Sohi, “Adaptive, Efficient, Parallel Execution of Parallel Programs,” 35th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’14), Edinburgh, UK, June 2014.
• G. Gupta, S. Sridharan, G. S. Sohi, “Globally Precise-restartable Execution of Parallel Programs,” 35th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’14), Edinburgh, UK, June 2014.
• S. Sridharan, G. Gupta, G. S. Sohi, “Holistic Run-time Parallelism Management for Time and Energy Efficiency,” 27th International Conference on Supercomputing (ICS’13), Eugene, OR, June 2013.
• G. Gupta and G. S. Sohi, “Dataflow Execution of Sequential Imperative Programs on Multicore Architectures,” 44th Annual International Symposium on Microarchitecture (MICRO-44), Dec. 2011.
• P. M. Wells, K. Chakraborty, and G. S. Sohi, “Mixed-Mode Multicore Reliability,” 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIV), Washington, DC, March 2009.
• M. D. Allen, S. Sridharan and G. S. Sohi, “Serialization Sets: A Dynamic Dependence-Based Parallel Execution Model,” in Proceedings of the 14th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP '09), Raleigh, NC, Feb. 2009.
• P. M. Wells, K. Chakraborty, and G. S. Sohi, “Adapting to Intermittent Faults in Multicore Systems,” 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIII), Seattle, Washington, March 2008.
• P. M. Wells and G. S. Sohi, “Serializing Instruction in System-Intensive Workloads: Amdahl's Law Strikes Again,” in Proeedings. of the 14th International Symposium on High-Performance Computer Architecture (HPCA-08), Salt Lake City, UT, Feb. 2008.
• J. Chang and G. S. Sohi, “Cooperative cache partitioning for chip multiprocessors,” Int. Conference on Supercomputing (ICS ’07), Seattle, Washington, June 2007.
• K. Chakraborty, P. M. Wells and G. S. Sohi, “Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly,” 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), San Jose, California, Oct 2006.
• P. M. Wells, K. Chakraborty and G. S. Sohi, “Hardware Support for Spin Management in Overcommitted Virtual Machines,” in Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT-2006), Seattle, Washington, pp. 124-133, September 2006.
• J. Chang and G. S. Sohi, “Cooperative Caching for Chip Multiprocessors,” in 33rd Int. Symposium on Computer Architecture (ISCA-33), Boston, Massachusetts, pp. 264-275, June 2006.
• S. Balakrishnan and G. S. Sohi, “Program De-multiplexing: Data-flow based Speculative Execution of Methods in Sequential Programs,” in 33rd Int. Symposium on Computer Architecture (ISCA-33), Boston, Massachusetts, pp. 302-313, June 2006.
• J. Huh, J. Chang, D. Burger, G. S. Sohi, “Coherence Decoupling: Making Use of Incoherence,” 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), Oct 2004, pp. 97-106.
• J. Adam Butts and G. S. Sohi, “Use-Based Register Caching with Decoupled Indexing,” 31th Int. Symposium on Computer Architecture (ISCA-31), June 2004.
• S. Balakrishnan and G. S. Sohi, “Exploiting Value Locality in Physical Register Files,” 36th Annual International Symposium on Microarchitecture (MICRO-36), Dec. 2003.
• P. S. Oberoi and G. S. Sohi, “Parallelism in the Front-End,” 30th Int. Symposium on Computer Architecture (ISCA-30), San Diego, California, June 2003.
• J. Adam Butts and G. S. Sohi, “Characterizing and Predicting Value Degree of Use,” 35th Annual International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
• A. Roth and G. S. Sohi, “A Quantitative Framework for Automated Pre-Execution Thread Selection,” 35th Annual International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
• C. B. Zilles and G. S. Sohi, “Master/Slave Speculative Parallelization,” 35th Annual International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
• J. Adam Butts and G. S. Sohi, “Dynamic Dead-Instruction Detection and Elimination,” 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), Oct 2002.
• P. S. Oberoi and G. S. Sohi, “Out-of-Order Fetch Using Multiple Sequencers,” International Conference on Parallel Processing (ICPP), August 2002
• C. B. Zilles and G. S. Sohi, “Execution-based Prediction Using Speculative Slices,” 28th Int. Symposium on Computer Architecture (ISCA-28), Gotenberg, Sweden, July 2001.
• A. Roth and G. S. Sohi, “Speculative Data-Driven Multithreading,” 7th Int. Symposium on High Performance Computer Architecture (HPCA-7), Jan. 2001.
• C. B. Zilles and G. S. Sohi, “A Programmable Co-processor for Profiling,”7th Int. Symposium on High Performance Computer Architecture (HPCA-7), Jan. 2001.
• J. Adam Butts and G. S. Sohi, “A Static Power Model for Architects,” 33rd Annual International Symposium on Microarchitecture (MICRO-33), Dec. 2000.
• A. Roth and G. S. Sohi, “Register Integration: A Simple and Efficient Implementation of Squash Reuse,” 33rd Annual International Symposium on Microarchitecture (MICRO-33), Dec. 2000.
• C. B. Zilles and G. S. Sohi, “Understanding the Backward Slices of Long Latency Events,” 27th Int. Symposium on Computer Architecture (ISCA-27), Vancouver, Canada, June 2000.
• A. Moshovos and G. S. Sohi, “Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors,” 6th Int. Symposium on High Performance Computer Architecture (HPCA-6), Jan. 2000.
• A. Moshovos and G. S. Sohi, “Read-After-Read Memory Dependence Prediction,” 32st Annual International Symposium on Microarchitecture (MICRO-32), Nov. 1999.
• C. Zilles, J. Emer, and G. S. Sohi, “The Use of Multithreading for Software Exception Handling,” 32st Annual International Symposium on Microarchitecture (MICRO-32), Nov. 1999.
• A. Roth and G. S. Sohi, “Improving Virtual Function Target Call Prediction via Dependence-Based Precomputation,” Int. Conference on Supercomputing (ICS ’99), Rhodes, Greece, June 1999.
• A. Roth and G. S. Sohi, “Effective Jump Pointer Prefetching for Linked Data Structures,” in 26th Int. Symposium on Computer Architecture (ISCA-26), Atlanta, Georgia, May 1999.
• T. N. Vijaykumar and G. S. Sohi, “Task Partitioning for the Multiscalar Architecture,” 31st Annual International Symposium on Microarchitecture (MICRO-31), Dec. 1998.
• A. Sodani and G. S. Sohi, “Understanding the Differences Between Value Prediction and Instruction Reuse,” 31st Annual International Symposium on Microarchitecture (MICRO-31), Dec. 1998.
• A. Sodani and G. S. Sohi, “An Empirical Analysis of Instruction Repetition,” 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998.
• A. Roth, A. Moshovos, and G. S. Sohi, “Dependence Based Prefetching for Linked Data Structures,” 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998.
• S. Gopal, T.N. Vijaykumar, J. E. Smith and G. S. Sohi, “Speculative Versioning Cache,” 4th Int. Symposium on High Performance Computer Architecture (HPCA-4), Feb. 1998.
• A. Moshovos and G. S. Sohi, “Streamlining Inter-operation Memory Communication via Data Dependence Prediction,” 30th Annual international Symposium on Microarchitecture (MICRO-30), Dec. 1997.
• A. Sodani and G. S. Sohi, “Dynamic Instruction Reuse,” in 24th Int. Symposium on Computer Architecture (ISCA-24), Denver, Colorado, June 1997.
• A. Moshovos, S. E. Breach, T.N. Vijaykumar, and G. S. Sohi, “Dynamic Speculation and Synchronization of Data Dependences,” in 24th Int. Symposium on Computer Architecture (ISCA-24) Denver, Colorado, June 1997.
• T. M. Austin and G. S. Sohi, “High-Bandwidth Address Translation for Multiple-Issue Processors,” 23th Int. Symposium on Computer Architecture (ISCA-23), Philadelphia, Pennsylvania, May 1996.
• T. M. Austin and G. S. Sohi, “Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency,” 28th Annual Int. Symposium on Microarchitecture (MICRO-28), Ann Arbor, Michigan, December 1995.
• G. S. Sohi, S. E. Breach, and T. N. Vijaykumar, “Multiscalar Processors,” 22th Int. Symposium on Computer Architecture (ISCA-22), Santa Margherita Ligure, Italy, June 1995.
• T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi, “Streamlining Data Cache Access with Fast Address Calculation,” 22th Int. Symposium on Computer Architecture (ISCA-22), Santa Margherita Ligure, Italy, June 1995.
• S. E. Breach, T. N. Vijaykumar, and G. S. Sohi, “The Anatomy of the Register File in a Multiscalar Processor,” 27th Annual Int. Symposium on Microarchitecture (MICRO-27), San Jose, California, December 1994.
• T. M. Austin, S. E. Breach, and G. S. Sohi, “Efficient Detection of All Pointer and Array Access Errors,” SIGPLAN ’94 Conference on Programming Language Design and Implementation, Orlando, Florida, June 1994.
• D. Pnevmatikatos and G. S. Sohi, “Guarded Execution and Branch Prediction in Dynamic ILP Processors,” 21th Int. Symposium on Computer Architecture (ISCA-21), Chicago, Illinois, April 1994.
• D. Pnevmatikatos, M. Franklin, and G. S. Sohi, “Control Flow Prediction for Dynamic ILP Processors,” 26th Annual Int. Symposium on Microarchitecture (MICRO-26), Austin, Texas, December 1993.
• M. Franklin and G. S. Sohi, “Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors,” 25th Annual Int. Symposium on Microarchitecture (MICRO-25), Portland, Oregon, December 1992.
• M. Franklin and G. S. Sohi, “The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,” 19th Int. Symposium on Computer Architecture (ISCA-19), Queensland, Australia, May 1992.
• T. M. Austin and G. S. Sohi, “Dynamic Dependency Analysis of Ordinary Programs,” 19th Int. Symposium on Computer Architecture (ISCA-19), Queensland, Australia, May 1992.
• S. Vajapeyam, G. S. Sohi and W.-C. Hsu, “An Empirical Study of the Cray Y-MP Processor Using the Perfect Club Benchmarks,” 18th Int. Symposium on Computer Architecture (ISCA-18), Toronto, Canada, May 1991.
• M.-C. Chiang and G. S. Sohi, “Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors,” SIGMETRICS ’91, San Diego, May 1991.
• G. S. Sohi and M. Franklin, “High Bandwidth Data Memory Systems for Superscalar Processors,” Fourth Int. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV), Santa Clara, April 1991.
• M. A. Friedman and G. S. Sohi, “An Architectural Characterization of Prolog Execution,” Int. Workshop on VLSI for Artificial Intelligence and Neural Networks, Oxford, England, September 1990.
• S. Vajapeyam, G. S. Sohi and W.-C. Hsu, “Exploitation of Instruction-Level Parallelism in a Cray X-MP Processor,” Int. Conference on Computer Design (ICCD 90), September 1990.
• V. S. Madan, C.-J. Peng and G. S. Sohi, “On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns,” North American Conference on Logic Programming (NACLP), Cleveland, Ohio, October 1989.
• G. S. Sohi, M. Franklin and K. K. Saluja, “A Study of Time-Redundant Fault Tolerance Techniques for High-Performance Pipelined Computers,” 19th Int. Symposium on Fault-Tolerant Computing (FTCS-19), Chicago, Illinois, June 1989.
• S. L. Scott and G. S. Sohi, “Using Feedback to Control Tree Saturation in Multistage Interconnection Networks,” 16th Int. Symposium on Computer Architecture (ISCA-16), Jerusalem, Israel, June 1989.
• G. S. Sohi, J. E. Smith and J. R. Goodman, “Restricted Fetch&Φ Operations for Parallel Processing,” Int. Conference on Supercomputing (ICS ’89), Crete, Greece, June 1989.
• G. S. Sohi and S. Vajapeyam, “Tradeoffs in Instruction Format Design for Horizontal Architectures,” Third Int. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-III), Boston, April 1989.
• M. K. Vernon, R. Jog and G. S. Sohi, “Performance Analysis of Hierarchical Cache-Coherent Multiprocessors,” Int. Seminar on Performance of Distributed and Parallel Systems, Kyoto, Japan, December 1988.
• A. R. Pleszkun and G. S. Sohi, “Multiple Instruction Issue and Single-Chip Processors,” 21st Annual Workshop on Microprogramming and Microarchitecture (MICRO-21), San Diego, California, December 1988.
• G. S. Sohi, “Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors,” Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Springfield, Massachusetts, October 1988.
• A. R. Pleszkun and G. S. Sohi, “The Performance Potential of Multiple Functional Unit Processors,” 15th Int. Symposium on Computer Architecturem (ISCA-15), Honolulu, June 1988.
• K. Cheung, G. S. Sohi, K. Saluja and D. Pradhan, “Organization and Analysis of a Gracefully-Degrading Interleaved Memory System,” 14th Int. Symposium on Computer Architecture (ISCA-14), Pittsburgh, June 1987.
• G. S. Sohi and S. Vajapeyam, “Instruction Issue Logic for High-Performance, Interruptible Pipelined Processors,” 14th Int. Symposium on Computer Architecture (ISCA-14), Pittsburgh, June 1987.
• G. S. Sohi, E. S. Davidson and J. H. Patel, “An Efficient LISP-execution Architecture with a New Representation for List Structures,” 12th Int. Symposium on Computer Architecture (ISCA-12), Boston, June 1985.
• G. S. Sohi and E. S. Davidson, “Performance of the Structured Memory Access (SMA) Architecture,” 1984 Int. Conference on Parallel Processing (ICPP), August 1984.