29 #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
30 #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
32 #include <unordered_map>
34 #include "mem/protocol/AccessPermission.hh"
47 operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
83 void print(std::ostream& out)
const;
91 std::unordered_map<Addr, PerfectCacheLineState<ENTRY> >
m_map;
96 operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
103 template<
class ENTRY>
110 template<
class ENTRY>
117 template<
class ENTRY>
126 template<
class ENTRY>
137 template<
class ENTRY>
145 template<
class ENTRY>
149 panic(
"cacheProbe called in perfect cache");
154 template<
class ENTRY>
162 template<
class ENTRY>
169 template<
class ENTRY>
170 inline AccessPermission
176 template<
class ENTRY>
179 AccessPermission new_perm)
186 template<
class ENTRY>
192 #endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
bool cacheAvail(Addr address) const
void allocate(Addr address)
ENTRY * lookup(Addr address)
std::unordered_map< Addr, PerfectCacheLineState< ENTRY > > m_map
bool isTagPresent(Addr address) const
void deallocate(Addr address)
Addr cacheProbe(Addr newAddress) const
AccessPermission m_permission
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
AccessPermission getPermission(Addr address) const
Addr makeLineAddress(Addr addr)
void print(std::ostream &out) const
void changePermission(Addr address, AccessPermission new_perm)
PerfectCacheMemory & operator=(const PerfectCacheMemory &obj)