gpu_types.hh

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/*
 * Copyright (c) 2015 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * For use for simulation and test purposes only
 *
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 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
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 * may be used to endorse or promote products derived from this software
 * without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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 * Author: Anthony Gutierrez
 */

#ifndef __ARCH_HSAIL_GPU_TYPES_HH__
#define __ARCH_HSAIL_GPU_TYPES_HH__

#include <cstdint>

namespace Brig
{
    class BrigInstBase;
}

class BrigObject;

namespace HsailISA
{
    // A raw machine instruction represents the raw bits that
    // our model uses to represent an actual instruction. In
    // the case of HSAIL this is just an index into a list of
    // instruction objects.
    typedef uint32_t RawMachInst;

    // The MachInst is a representation of an instruction
    // that has more information than just the machine code.
    // For HSAIL the actual machine code is a BrigInstBase
    // and the BrigObject contains more pertinent
    // information related to operaands, etc.

    struct MachInst
    {
        const Brig::BrigInstBase *brigInstBase;
        const BrigObject *brigObj;
    };
}

#endif // __ARCH_HSAIL_GPU_TYPES_HH__