gem5
|
#include <algorithm>
#include <cstring>
#include <map>
#include <queue>
#include "arch/generic/debugfaults.hh"
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
Go to the source code of this file.
Classes | |
class | LSQUnit< Impl > |
Class that implements the actual LQ and SQ for each specific thread. More... | |
class | LSQUnit< Impl >::LSQSenderState |
Derived class to hold any sender state the LSQ needs. More... | |
class | LSQUnit< Impl >::WritebackEvent |
Writeback event, specifically for when stores forward data to loads. More... | |
struct | LSQUnit< Impl >::SQEntry |