#include "arch/mips/generated/max_inst_regs.hh"
#include "base/misc.hh"
#include "base/types.hh"

Go to the source code of this file.

Classes
union	MipsISA::AnyReg

Namespaces
	MipsISA

Typedefs
typedef uint16_t	MipsISA::RegIndex

typedef uint32_t	MipsISA::IntReg

typedef uint32_t	MipsISA::FloatRegBits

typedef float	MipsISA::FloatReg

typedef uint64_t	MipsISA::MiscReg

typedef uint8_t	MipsISA::CCReg

Enumerations
enum	MipsISA::FPControlRegNums { MipsISA::FLOATREG_FIR = NumFloatArchRegs, MipsISA::FLOATREG_FCCR, MipsISA::FLOATREG_FEXR, MipsISA::FLOATREG_FENR, MipsISA::FLOATREG_FCSR }

enum	MipsISA::FCSRBits { MipsISA::Inexact = 1, MipsISA::Underflow, MipsISA::Overflow, MipsISA::DivideByZero, MipsISA::Invalid, MipsISA::Unimplemented }

enum	MipsISA::FCSRFields { MipsISA::Flag_Field = 1, MipsISA::Enable_Field = 6, MipsISA::Cause_Field = 11 }

enum	MipsISA::MiscIntRegNums { MipsISA::INTREG_LO = NumIntArchRegs, MipsISA::INTREG_DSP_LO0 = INTREG_LO, MipsISA::INTREG_HI, MipsISA::INTREG_DSP_HI0 = INTREG_HI, MipsISA::INTREG_DSP_ACX0, MipsISA::INTREG_DSP_LO1, MipsISA::INTREG_DSP_HI1, MipsISA::INTREG_DSP_ACX1, MipsISA::INTREG_DSP_LO2, MipsISA::INTREG_DSP_HI2, MipsISA::INTREG_DSP_ACX2, MipsISA::INTREG_DSP_LO3, MipsISA::INTREG_DSP_HI3, MipsISA::INTREG_DSP_ACX3, MipsISA::INTREG_DSP_CONTROL }

enum	MipsISA::MiscRegIndex { MipsISA::MISCREG_INDEX = 0, MipsISA::MISCREG_MVP_CONTROL, MipsISA::MISCREG_MVP_CONF0, MipsISA::MISCREG_MVP_CONF1, MipsISA::MISCREG_CP0_RANDOM = 8, MipsISA::MISCREG_VPE_CONTROL, MipsISA::MISCREG_VPE_CONF0, MipsISA::MISCREG_VPE_CONF1, MipsISA::MISCREG_YQMASK, MipsISA::MISCREG_VPE_SCHEDULE, MipsISA::MISCREG_VPE_SCHEFBACK, MipsISA::MISCREG_VPE_OPT, MipsISA::MISCREG_ENTRYLO0 = 16, MipsISA::MISCREG_TC_STATUS, MipsISA::MISCREG_TC_BIND, MipsISA::MISCREG_TC_RESTART, MipsISA::MISCREG_TC_HALT, MipsISA::MISCREG_TC_CONTEXT, MipsISA::MISCREG_TC_SCHEDULE, MipsISA::MISCREG_TC_SCHEFBACK, MipsISA::MISCREG_ENTRYLO1 = 24, MipsISA::MISCREG_CONTEXT = 32, MipsISA::MISCREG_CONTEXT_CONFIG, MipsISA::MISCREG_PAGEMASK = 40, MipsISA::MISCREG_PAGEGRAIN = 41, MipsISA::MISCREG_WIRED = 48, MipsISA::MISCREG_SRS_CONF0, MipsISA::MISCREG_SRS_CONF1, MipsISA::MISCREG_SRS_CONF2, MipsISA::MISCREG_SRS_CONF3, MipsISA::MISCREG_SRS_CONF4, MipsISA::MISCREG_HWRENA = 56, MipsISA::MISCREG_BADVADDR = 64, MipsISA::MISCREG_COUNT = 72, MipsISA::MISCREG_ENTRYHI = 80, MipsISA::MISCREG_COMPARE = 88, MipsISA::MISCREG_STATUS = 96, MipsISA::MISCREG_INTCTL, MipsISA::MISCREG_SRSCTL, MipsISA::MISCREG_SRSMAP, MipsISA::MISCREG_CAUSE = 104, MipsISA::MISCREG_EPC = 112, MipsISA::MISCREG_PRID = 120, MipsISA::MISCREG_EBASE, MipsISA::MISCREG_CONFIG = 128, MipsISA::MISCREG_CONFIG1, MipsISA::MISCREG_CONFIG2, MipsISA::MISCREG_CONFIG3, MipsISA::MISCREG_CONFIG4, MipsISA::MISCREG_CONFIG5, MipsISA::MISCREG_CONFIG6, MipsISA::MISCREG_CONFIG7, MipsISA::MISCREG_LLADDR = 136, MipsISA::MISCREG_WATCHLO0 = 144, MipsISA::MISCREG_WATCHLO1, MipsISA::MISCREG_WATCHLO2, MipsISA::MISCREG_WATCHLO3, MipsISA::MISCREG_WATCHLO4, MipsISA::MISCREG_WATCHLO5, MipsISA::MISCREG_WATCHLO6, MipsISA::MISCREG_WATCHLO7, MipsISA::MISCREG_WATCHHI0 = 152, MipsISA::MISCREG_WATCHHI1, MipsISA::MISCREG_WATCHHI2, MipsISA::MISCREG_WATCHHI3, MipsISA::MISCREG_WATCHHI4, MipsISA::MISCREG_WATCHHI5, MipsISA::MISCREG_WATCHHI6, MipsISA::MISCREG_WATCHHI7, MipsISA::MISCREG_XCCONTEXT64 = 160, MipsISA::MISCREG_DEBUG = 184, MipsISA::MISCREG_TRACE_CONTROL1, MipsISA::MISCREG_TRACE_CONTROL2, MipsISA::MISCREG_USER_TRACE_DATA, MipsISA::MISCREG_TRACE_BPC, MipsISA::MISCREG_DEPC = 192, MipsISA::MISCREG_PERFCNT0 = 200, MipsISA::MISCREG_PERFCNT1, MipsISA::MISCREG_PERFCNT2, MipsISA::MISCREG_PERFCNT3, MipsISA::MISCREG_PERFCNT4, MipsISA::MISCREG_PERFCNT5, MipsISA::MISCREG_PERFCNT6, MipsISA::MISCREG_PERFCNT7, MipsISA::MISCREG_ERRCTL = 208, MipsISA::MISCREG_CACHEERR0 = 216, MipsISA::MISCREG_CACHEERR1, MipsISA::MISCREG_CACHEERR2, MipsISA::MISCREG_CACHEERR3, MipsISA::MISCREG_TAGLO0 = 224, MipsISA::MISCREG_DATALO1, MipsISA::MISCREG_TAGLO2, MipsISA::MISCREG_DATALO3, MipsISA::MISCREG_TAGLO4, MipsISA::MISCREG_DATALO5, MipsISA::MISCREG_TAGLO6, MipsISA::MISCREG_DATALO7, MipsISA::MISCREG_TAGHI0 = 232, MipsISA::MISCREG_DATAHI1, MipsISA::MISCREG_TAGHI2, MipsISA::MISCREG_DATAHI3, MipsISA::MISCREG_TAGHI4, MipsISA::MISCREG_DATAHI5, MipsISA::MISCREG_TAGHI6, MipsISA::MISCREG_DATAHI7, MipsISA::MISCREG_ERROR_EPC = 240, MipsISA::MISCREG_DESAVE = 248, MipsISA::MISCREG_LLFLAG = 257, MipsISA::MISCREG_TP_VALUE, MipsISA::MISCREG_NUMREGS }

Variables
const int	MipsISA::NumIntArchRegs = 32

const int	MipsISA::NumIntSpecialRegs = 9

const int	MipsISA::NumFloatArchRegs = 32

const int	MipsISA::NumFloatSpecialRegs = 5

const int	MipsISA::MaxShadowRegSets = 16

const int	MipsISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

const int	MipsISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

const int	MipsISA::NumCCRegs = 0

const uint32_t	MipsISA::MIPS32_QNAN = 0x7fbfffff

const uint64_t	MipsISA::MIPS64_QNAN = ULL(0x7ff7ffffffffffff)

const int	MipsISA::ZeroReg = 0

const int	MipsISA::AssemblerReg = 1

const int	MipsISA::SyscallSuccessReg = 7

const int	MipsISA::FirstArgumentReg = 4

const int	MipsISA::ReturnValueReg = 2

const int	MipsISA::KernelReg0 = 26

const int	MipsISA::KernelReg1 = 27

const int	MipsISA::GlobalPointerReg = 28

const int	MipsISA::StackPointerReg = 29

const int	MipsISA::FramePointerReg = 30

const int	MipsISA::ReturnAddressReg = 31

const int	MipsISA::SyscallPseudoReturnReg = 3

const int	MipsISA::NumMiscRegs = MISCREG_NUMREGS

const int	MipsISA::FP_Reg_Base = NumIntRegs

const int	MipsISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs

const int	MipsISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs

const int	MipsISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs

const int	MipsISA::TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs

Classes

Namespaces

Typedefs

Enumerations

Variables