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decoder.hh
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40  * Authors: Gabe Black
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42 
43 #ifndef __ARCH_ARM_DECODER_HH__
44 #define __ARCH_ARM_DECODER_HH__
45 
46 #include <cassert>
47 
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "enums/DecoderFlavour.hh"
54 
55 namespace ArmISA
56 {
57 
58 class ISA;
59 class Decoder
60 {
61  protected:
62  //The extended machine instruction being generated
65  bool bigThumb;
66  bool instDone;
67  bool outOfBytes;
68  int offset;
69  bool foundIt;
70  ITSTATE itBits;
71 
72  int fpscrLen;
74 
75  Enums::DecoderFlavour decoderFlavour;
76 
79 
84  void process();
85 
90  void consumeBytes(int numBytes);
91 
92  public: // Decoder API
93  Decoder(ISA* isa = nullptr);
94 
96  void reset();
97 
105  bool needMoreBytes() const { return outOfBytes; }
106 
115  bool instReady() const { return instDone; }
116 
143  void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
144 
157 
168  {
169  return defaultCache.decode(this, mach_inst, addr);
170  }
171 
185 
191  void takeOverFrom(Decoder *old) {}
192 
193 
194  public: // ARM-specific decoder state manipulation
195  void setContext(FPSCR fpscr)
196  {
197  fpscrLen = fpscr.len;
198  fpscrStride = fpscr.stride;
199  }
200 };
201 
202 } // namespace ArmISA
203 
204 #endif // __ARCH_ARM_DECODER_HH__
uint32_t MachInst
Definition: types.hh:54
ip6_addr_t addr
Definition: inet.hh:335
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:143
void takeOverFrom(Decoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:191
Some registers alias with others, and therefore need to be translated.
Definition: isa.cc:67
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:76
ITSTATE itBits
Definition: decoder.hh:70
MachInst data
Definition: decoder.hh:64
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:78
bool outOfBytes
Definition: decoder.hh:67
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
Definition: decoder.cc:170
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:42
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
uint64_t ExtMachInst
Definition: types.hh:41
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:167
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
Definition: decoder.cc:152
Enums::DecoderFlavour decoderFlavour
Definition: decoder.hh:75
bool instReady() const
Is an instruction ready to be decoded?
Definition: decoder.hh:115
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
bool needMoreBytes() const
Can the decoder accept more data?
Definition: decoder.hh:105
IntReg pc
Definition: remote_gdb.hh:91
Decoder(ISA *isa=nullptr)
Definition: decoder.cc:56
void reset()
Reset the decoders internal state.
Definition: decoder.cc:65
ExtMachInst emi
Definition: decoder.hh:63
void setContext(FPSCR fpscr)
Definition: decoder.hh:195

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