tlb.hh

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/*
 * Copyright (c) 2011 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * Authors: Gabe Black
 */

#ifndef __ARCH_GENERIC_TLB_HH__
#define __ARCH_GENERIC_TLB_HH__

#include "base/misc.hh"
#include "mem/request.hh"
#include "sim/sim_object.hh"

class ThreadContext;
class BaseMasterPort;

class BaseTLB : public SimObject
{
  protected:
    BaseTLB(const Params *p)
        : SimObject(p)
    {}

  public:
    enum Mode { Read, Write, Execute };

  public:
    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;

    virtual void flushAll() = 0;

    virtual void takeOverFrom(BaseTLB *otlb) = 0;

    virtual BaseMasterPort* getMasterPort() { return NULL; }

    void memInvalidate() { flushAll(); }

    class Translation
    {
      public:
        virtual ~Translation()
        {}

        virtual void markDelayed() = 0;

        /*
         * The memory for this object may be dynamically allocated, and it may
         * be responsible for cleaning itself up which will happen in this
         * function. Once it's called, the object is no longer valid.
         */
        virtual void finish(const Fault &fault, RequestPtr req,
                            ThreadContext *tc, Mode mode) = 0;

        virtual bool squashed() const { return false; }
    };
};

class GenericTLB : public BaseTLB
{
  protected:
    GenericTLB(const Params *p)
        : BaseTLB(p)
    {}

  public:
    void demapPage(Addr vaddr, uint64_t asn) override;

    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
    void translateTiming(RequestPtr req, ThreadContext *tc,
                         Translation *translation, Mode mode);


    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
};

#endif // __ARCH_GENERIC_TLB_HH__