base.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2005 The Regents of The University of Michigan
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * Authors: Ron Dreslinski
 *          Mitch Hayenga
 */

#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
#define __MEM_CACHE_PREFETCH_BASE_HH__

#include "base/statistics.hh"
#include "mem/packet.hh"
#include "params/BasePrefetcher.hh"
#include "sim/clocked_object.hh"

class BaseCache;

class BasePrefetcher : public ClockedObject
{
  protected:

    // PARAMETERS

    BaseCache* cache;

    unsigned blkSize;

    unsigned lBlkSize;

    System* system;

    bool onMiss;

    bool onRead;

    bool onWrite;

    bool onData;

    bool onInst;

    MasterID masterId;

    const Addr pageBytes;

    bool observeAccess(const PacketPtr &pkt) const;

    bool inCache(Addr addr, bool is_secure) const;

    bool inMissQueue(Addr addr, bool is_secure) const;

    bool samePage(Addr a, Addr b) const;
    Addr blockAddress(Addr a) const;
    Addr blockIndex(Addr a) const;
    Addr pageAddress(Addr a) const;
    Addr pageOffset(Addr a) const;
    Addr pageIthBlockAddress(Addr page, uint32_t i) const;


    Stats::Scalar pfIssued;

  public:

    BasePrefetcher(const BasePrefetcherParams *p);

    virtual ~BasePrefetcher() {}

    void setCache(BaseCache *_cache);

    virtual Tick notify(const PacketPtr &pkt) = 0;

    virtual PacketPtr getPacket() = 0;

    virtual Tick nextPrefetchReadyTime() const = 0;

    virtual void regStats();
};
#endif //__MEM_CACHE_PREFETCH_BASE_HH__