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pagetable_walker.hh
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37  * Authors: Gabe Black
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39 
40 #ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
41 #define __ARCH_X86_PAGE_TABLE_WALKER_HH__
42 
43 #include <vector>
44 
45 #include "arch/x86/pagetable.hh"
46 #include "arch/x86/tlb.hh"
47 #include "base/types.hh"
48 #include "mem/mem_object.hh"
49 #include "mem/packet.hh"
50 #include "params/X86PagetableWalker.hh"
51 #include "sim/faults.hh"
52 #include "sim/system.hh"
53 
54 class ThreadContext;
55 
56 namespace X86ISA
57 {
58  class Walker : public MemObject
59  {
60  protected:
61  // Port for accessing memory
62  class WalkerPort : public MasterPort
63  {
64  public:
65  WalkerPort(const std::string &_name, Walker * _walker) :
66  MasterPort(_name, _walker), walker(_walker)
67  {}
68 
69  protected:
71 
72  bool recvTimingResp(PacketPtr pkt);
73  void recvReqRetry();
74  };
75 
76  friend class WalkerPort;
78 
79  // State to track each walk of the page table
81  {
82  friend class Walker;
83  private:
84  enum State {
87  // Long mode
89  // PAE legacy mode
91  // Non PAE legacy mode with and without PSE
93  };
94 
95  protected:
101  int dataSize;
102  bool enableNX;
103  unsigned inflight;
111  bool timing;
112  bool retrying;
113  bool started;
114  public:
115  WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
116  RequestPtr _req, bool _isFunctional = false) :
117  walker(_walker), req(_req), state(Ready),
118  nextState(Ready), inflight(0),
119  translation(_translation),
120  functional(_isFunctional), timing(false),
121  retrying(false), started(false)
122  {
123  }
124  void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
125  bool _isTiming = false);
126  Fault startWalk();
127  Fault startFunctional(Addr &addr, unsigned &logBytes);
128  bool recvPacket(PacketPtr pkt);
129  bool isRetrying();
130  bool wasStarted();
131  bool isTiming();
132  void retry();
133  std::string name() const {return walker->name();}
134 
135  private:
136  void setupWalk(Addr vaddr);
137  Fault stepWalk(PacketPtr &write);
138  void sendPackets();
139  void endWalk();
140  Fault pageFault(bool present);
141  };
142 
143  friend class WalkerState;
144  // State for timing and atomic accesses (need multiple per walker in
145  // the case of multiple outstanding requests in timing mode)
147  // State for functional accesses (only need one of these per walker)
149 
151  {
154  senderWalk(_senderWalk) {}
155  };
156 
157  public:
158  // Kick off the state machine.
159  Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
162  unsigned &logBytes, BaseTLB::Mode mode);
163  BaseMasterPort &getMasterPort(const std::string &if_name,
164  PortID idx = InvalidPortID);
165 
166  protected:
167  // The TLB we're supposed to load.
168  TLB * tlb;
171 
172  // The number of outstanding walks that can be squashed per cycle.
173  unsigned numSquashable;
174 
175  // Wrapper for checking for squashes before starting a translation.
176  void startWalkWrapper();
177 
182 
183  // Functions for dealing with packets.
184  bool recvTimingResp(PacketPtr pkt);
185  void recvReqRetry();
186  bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
187 
188  public:
189 
190  void setTLB(TLB * _tlb)
191  {
192  tlb = _tlb;
193  }
194 
195  typedef X86PagetableWalkerParams Params;
196 
197  const Params *
198  params() const
199  {
200  return static_cast<const Params *>(_params);
201  }
202 
203  Walker(const Params *params) :
204  MemObject(params), port(name() + ".port", this),
205  funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
206  masterId(sys->getMasterId(name())),
207  numSquashable(params->num_squash_per_cycle),
209  {
210  }
211  };
212 }
213 #endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:167
unsigned logBytes
Definition: pagetable.hh:107
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
bool recvPacket(PacketPtr pkt)
const PortID InvalidPortID
Definition: types.hh:182
X86PagetableWalkerParams Params
Walker(const Params *params)
const Params * params() const
MemObject declaration.
WalkerSenderState(WalkerState *_senderWalk)
WalkerPort(const std::string &_name, Walker *_walker)
Bitfield< 7 > present
Definition: misc.hh:945
Definition: system.hh:83
Bitfield< 4, 0 > mode
Definition: miscregs.hh:1385
TLB::Translation * translation
ThreadContext is the external interface to all thread state for anything outside of the CPU...
WalkerState funcState
STL vector class.
Definition: stl.hh:40
void setTLB(TLB *_tlb)
void initState(ThreadContext *_tc, BaseTLB::Mode _mode, bool _isTiming=false)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
Fault start(ThreadContext *_tc, BaseTLB::Translation *translation, RequestPtr req, BaseTLB::Mode mode)
Fault startFunctional(Addr &addr, unsigned &logBytes)
TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only)
STL list class.
Definition: stl.hh:54
EventWrapper< Walker,&Walker::startWalkWrapper > startWalkWrapperEvent
Event used to call startWalkWrapper.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
uint16_t MasterID
Definition: request.hh:85
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
Bitfield< 15 > system
Definition: misc.hh:950
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
Definition: packet.hh:377
Mode
Definition: tlb.hh:61
std::vector< PacketPtr > writes
virtual const std::string name() const
Definition: sim_object.hh:117
Declaration of the Packet class.
BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
EndBitUnion(PageTableEntry) struct TlbEntry Addr vaddr
Definition: pagetable.hh:96
Fault stepWalk(PacketPtr &write)
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
Definition: mem_object.hh:60
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
Definition: port.hh:115
std::list< WalkerState * > currStates
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:107
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:181
WalkerState(Walker *_walker, BaseTLB::Translation *_translation, RequestPtr _req, bool _isFunctional=false)
Fault pageFault(bool present)
std::shared_ptr< FaultBase > Fault
Definition: types.hh:184
Bitfield< 3 > addr
Definition: types.hh:81
bool recvTimingResp(PacketPtr pkt)

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