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Enforced rule for all verilog submissions
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Every verilog file must define EXACTLY one module. If you define multiple modules in a verilog file, it will be considered a violation of cs552 verilog rules.
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If a verilog file is called xor15.v, the module it contains must be named xor15.v
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The filename and module name must have an EXACT one-to-one match
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YOU CANNOT have a file called 15xor.v and in it create a module called adder.v
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Run the name-convention-check script
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Any instantiation of a module must include port names along with net-names.i.e
clkrst c0(clk, rst) is NOT OK
clkrst c0(.clk(clk), .rst(rst)) is CORRECT
Recommended Hierarchy and Filenaming conventions (For HW2-HW5 and project demos)
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For example, your top-level module must be called foo_hier.v
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It MUST contain clkrst.v
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Its interface (input/output ports) should be identical to what is suggested in your homework problems
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Name the module you are designing foo and instantiate foo inside foo_hier.v
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See example rf_hier.v and rf.v for examples for the register file (NOTE: These links are not set yet, but will be soon).
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You will follow a similar convention for your project.
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Create cpu.v and cpu_hier.v
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Name all testbenches with the _bench suffix
For project.
We will follow this same convention for your project.
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Your top most level with just the processor MUST be called proc.v. A template for will be provided for this.
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You must use the to-be-provided proc_hier.v which will instantiate the clock generator and your processor.
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You must use the to-be-provided proc_hier_bench.v testbench. If you cannot absolutely use this, email the instructor and TA to find a solution.
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