_currPwrState | ClockedObject | protected |
_params | SimObject | protected |
AbstractController(const Params *p) | AbstractController | |
alreadyScheduled(Tick time) | Consumer | inline |
blockOnQueue(Addr, MessageBuffer *) | AbstractController | |
ckptCount | Serializable | static |
ckptMaxCount | Serializable | static |
ckptPrevCount | Serializable | static |
Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
Clocked(Clocked &)=delete | Clocked | protected |
clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
clockPeriod() const | Clocked | inline |
collateStats() | AbstractController | inlinevirtual |
computeStats() | ClockedObject | |
Consumer(ClockedObject *_em) | Consumer | inline |
curCycle() const | Clocked | inline |
currentSection() | Serializable | static |
cyclesToTicks(Cycles c) const | Clocked | inline |
deschedule(Event &event) | EventManager | inline |
deschedule(Event *event) | EventManager | inline |
drain() override | SimObject | inlinevirtual |
Drainable() | Drainable | protected |
drainResume() | Drainable | inlineprotectedvirtual |
drainState() const | Drainable | inline |
enqueuePrefetch(const Addr &, const RubyRequestType &) | AbstractController | inlinevirtual |
EventManager(EventManager &em) | EventManager | inline |
EventManager(EventManager *em) | EventManager | inline |
EventManager(EventQueue *eq) | EventManager | inline |
eventq | EventManager | protected |
eventQueue() const | EventManager | inline |
find(const char *name) | SimObject | static |
frequency() const | Clocked | inline |
functionalMemoryRead(PacketPtr) | AbstractController | |
functionalMemoryWrite(PacketPtr) | AbstractController | |
functionalRead(const Addr &addr, PacketPtr)=0 | AbstractController | pure virtual |
functionalWrite(const Addr &addr, PacketPtr)=0 | AbstractController | pure virtual |
functionalWriteBuffers(PacketPtr &)=0 | AbstractController | pure virtual |
getAccessPermission(const Addr &addr)=0 | AbstractController | pure virtual |
getCPUSequencer() const =0 | AbstractController | pure virtual |
getDelayHist() | AbstractController | inline |
getDelayVCHist(uint32_t index) | AbstractController | inline |
getGPUCoalescer() const =0 | AbstractController | pure virtual |
getMachineID() const | AbstractController | inline |
getMandatoryQueue() const =0 | AbstractController | pure virtual |
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) | AbstractController | virtual |
getMemoryQueue() const =0 | AbstractController | pure virtual |
getProbeManager() | SimObject | |
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | MemObject | virtual |
getType() const | AbstractController | inline |
getVersion() const | AbstractController | inline |
init() | AbstractController | virtual |
initNetQueues()=0 | AbstractController | pure virtual |
initNetworkPtr(Network *net_ptr) | AbstractController | inline |
initState() | SimObject | virtual |
insertScheduledWakeupTime(Tick time) | Consumer | inline |
isBlocked(Addr) const | AbstractController | |
isBlocked(Addr) | AbstractController | |
loadState(CheckpointIn &cp) | SimObject | virtual |
m_block_map | AbstractController | protected |
m_buffer_size | AbstractController | protected |
m_clusterID | AbstractController | protected |
m_cur_in_port | AbstractController | protected |
m_delayHistogram | AbstractController | protected |
m_delayVCHistogram | AbstractController | protected |
m_fully_busy_cycles | AbstractController | protected |
m_in_ports | AbstractController | protected |
m_is_blocking | AbstractController | protected |
m_machineID | AbstractController | protected |
m_masterId | AbstractController | protected |
m_net_ptr | AbstractController | protected |
m_number_of_TBEs | AbstractController | protected |
m_recycle_latency | AbstractController | protected |
m_transitions_per_cycle | AbstractController | protected |
m_version | AbstractController | protected |
m_waiting_buffers | AbstractController | protected |
memInvalidate() | SimObject | inlinevirtual |
MemObject(const Params *params) | MemObject | |
memoryPort | AbstractController | protected |
memWriteback() | SimObject | inlinevirtual |
MsgBufType typedef | AbstractController | protected |
MsgVecType typedef | AbstractController | protected |
name() const | SimObject | inlinevirtual |
nextCycle() const | Clocked | inline |
notifyFork() | Drainable | inlinevirtual |
numPwrStateTransitions | ClockedObject | protected |
operator=(Clocked &)=delete | Clocked | protected |
Params typedef | AbstractController | |
params() const | AbstractController | inline |
print(std::ostream &out) const =0 | AbstractController | pure virtual |
profileMsgDelay(uint32_t virtualNetwork, Cycles delay) | AbstractController | protected |
profileRequest(const std::string &request) | AbstractController | protected |
prvEvalTick | ClockedObject | protected |
pwrState() const | ClockedObject | inline |
pwrState(Enums::PwrState) | ClockedObject | |
pwrStateClkGateDist | ClockedObject | protected |
pwrStateName() const | ClockedObject | inline |
pwrStateResidencyTicks | ClockedObject | protected |
pwrStateWeights() const | ClockedObject | |
queueMemoryRead(const MachineID &id, Addr addr, Cycles latency) | AbstractController | |
queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, const DataBlock &block) | AbstractController | |
queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, const DataBlock &block, int size) | AbstractController | |
recordCacheTrace(int cntrl, CacheRecorder *tr)=0 | AbstractController | pure virtual |
recvTimingResp(PacketPtr pkt) | AbstractController | |
regProbeListeners() | SimObject | virtual |
regProbePoints() | SimObject | virtual |
regStats() | AbstractController | virtual |
reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
resetClock() const | Clocked | inlineprotected |
resetStats()=0 | AbstractController | pure virtual |
schedule(Event &event, Tick when) | EventManager | inline |
schedule(Event *event, Tick when) | EventManager | inline |
scheduleEvent(Cycles timeDelta) | Consumer | protected |
scheduleEventAbsolute(Tick timeAbs) | Consumer | |
Serializable() | Serializable | |
serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
serializeAll(CheckpointOut &cp) | SimObject | static |
Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
setCurTick(Tick newVal) | EventManager | inline |
signalDrainDone() const | Drainable | inlineprotected |
SimObject(const Params *_params) | SimObject | |
stallBuffer(MessageBuffer *buf, Addr addr) | AbstractController | protected |
startup() | SimObject | virtual |
storeEventInfo(int info) | Consumer | inlinevirtual |
ticksToCycles(Tick t) const | Clocked | inline |
unblock(Addr) | AbstractController | |
unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
unserializeGlobals(CheckpointIn &cp) | Serializable | static |
unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
updateClockPeriod() const | Clocked | inline |
voltage() const | Clocked | inline |
WaitingBufType typedef | AbstractController | protected |
wakeup()=0 | AbstractController | pure virtual |
wakeUpAllBuffers(Addr addr) | AbstractController | protected |
wakeUpAllBuffers() | AbstractController | protected |
wakeUpBuffers(Addr addr) | AbstractController | protected |
wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
~Clocked() | Clocked | inlineprotectedvirtual |
~Consumer() | Consumer | inlinevirtual |
~Drainable() | Drainable | protectedvirtual |
~Serializable() | Serializable | virtual |
~SimObject() | SimObject | virtual |