| _params | SimObject | protected |
| BaseTLB(const Params *p) | BaseTLB | inlineprotected |
| checkCacheability(RequestPtr &req, bool itb=false) | AlphaISA::TLB | static |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| currentSection() | Serializable | static |
| data_accesses | AlphaISA::TLB | protected |
| data_acv | AlphaISA::TLB | protected |
| data_hits | AlphaISA::TLB | protected |
| data_misses | AlphaISA::TLB | protected |
| demapPage(Addr vaddr, uint64_t asn) override | AlphaISA::TLB | inlinevirtual |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| EntryCache | AlphaISA::TLB | |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| Execute enum value | BaseTLB | |
| fetch_accesses | AlphaISA::TLB | mutableprotected |
| fetch_acv | AlphaISA::TLB | mutableprotected |
| fetch_hits | AlphaISA::TLB | mutableprotected |
| fetch_misses | AlphaISA::TLB | mutableprotected |
| finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const | AlphaISA::TLB | |
| find(const char *name) | SimObject | static |
| flushAddr(Addr addr, uint8_t asn) | AlphaISA::TLB | |
| flushAll() override | AlphaISA::TLB | virtual |
| flushCache() | AlphaISA::TLB | inline |
| flushProcesses() | AlphaISA::TLB | |
| getMasterPort() | BaseTLB | inlinevirtual |
| getProbeManager() | SimObject | |
| getsize() const | AlphaISA::TLB | inline |
| index(bool advance=true) | AlphaISA::TLB | |
| init() | SimObject | virtual |
| initState() | SimObject | virtual |
| insert(Addr vaddr, TlbEntry &entry) | AlphaISA::TLB | |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lookup(Addr vpn, uint8_t asn) | AlphaISA::TLB | protected |
| lookupTable | AlphaISA::TLB | protected |
| memInvalidate() | BaseTLB | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| Mode enum name | BaseTLB | |
| name() const | SimObject | inlinevirtual |
| nextnlu() | AlphaISA::TLB | inlineprotected |
| nlu | AlphaISA::TLB | protected |
| notifyFork() | Drainable | inlinevirtual |
| PageTable typedef | AlphaISA::TLB | protected |
| Params typedef | AlphaISA::TLB | |
| params() const | SimObject | inline |
| Read enum value | BaseTLB | |
| read_accesses | AlphaISA::TLB | mutableprotected |
| read_acv | AlphaISA::TLB | mutableprotected |
| read_hits | AlphaISA::TLB | mutableprotected |
| read_misses | AlphaISA::TLB | mutableprotected |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() override | AlphaISA::TLB | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetStats() | SimObject | virtual |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | AlphaISA::TLB | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| startup() | SimObject | virtual |
| table | AlphaISA::TLB | protected |
| takeOverFrom(BaseTLB *otlb) override | AlphaISA::TLB | inlinevirtual |
| TLB(const Params *p) | AlphaISA::TLB | |
| translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) | AlphaISA::TLB | |
| translateData(RequestPtr req, ThreadContext *tc, bool write) | AlphaISA::TLB | protected |
| translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) | AlphaISA::TLB | |
| translateInst(RequestPtr req, ThreadContext *tc) | AlphaISA::TLB | protected |
| translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode) | AlphaISA::TLB | |
| unserialize(CheckpointIn &cp) override | AlphaISA::TLB | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateCache(TlbEntry *entry) | AlphaISA::TLB | inline |
| validVirtualAddress(Addr vaddr) | AlphaISA::TLB | inlinestatic |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| Write enum value | BaseTLB | |
| write_accesses | AlphaISA::TLB | mutableprotected |
| write_acv | AlphaISA::TLB | mutableprotected |
| write_hits | AlphaISA::TLB | mutableprotected |
| write_misses | AlphaISA::TLB | mutableprotected |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
| ~TLB() | AlphaISA::TLB | virtual |
