| _currPwrState | ClockedObject | protected |
| _params | SimObject | protected |
| accesses | BaseCache | |
| addrRanges | BaseCache | protected |
| allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send=true) | BaseCache | inline |
| allocateWriteBuffer(PacketPtr pkt, Tick time) | BaseCache | inline |
| allocOnFill(MemCmd cmd) const =0 | BaseCache | protectedpure virtual |
| avg_blocked | BaseCache | |
| avgMissLatency | BaseCache | |
| avgMshrMissLatency | BaseCache | |
| avgMshrUncacheableLatency | BaseCache | |
| BaseCache(const BaseCacheParams *p, unsigned blk_size) | BaseCache | |
| blkSize | BaseCache | protected |
| blocked | BaseCache | protected |
| blocked_causes | BaseCache | |
| blocked_cycles | BaseCache | |
| Blocked_NoMSHRs enum value | BaseCache | |
| Blocked_NoTargets enum value | BaseCache | |
| Blocked_NoWBBuffers enum value | BaseCache | |
| BlockedCause enum name | BaseCache | |
| blockedCycle | BaseCache | protected |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| clearBlocked(BlockedCause cause) | BaseCache | inline |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| computeStats() | ClockedObject | |
| cpuSidePort | BaseCache | protected |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| dataLatency | BaseCache | protected |
| demandAccesses | BaseCache | |
| demandAvgMissLatency | BaseCache | |
| demandAvgMshrMissLatency | BaseCache | |
| demandHits | BaseCache | |
| demandMisses | BaseCache | |
| demandMissLatency | BaseCache | |
| demandMissRate | BaseCache | |
| demandMshrHits | BaseCache | |
| demandMshrMisses | BaseCache | |
| demandMshrMissLatency | BaseCache | |
| demandMshrMissRate | BaseCache | |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| fillLatency | BaseCache | protected |
| find(const char *name) | SimObject | static |
| forwardLatency | BaseCache | protected |
| forwardSnoops | BaseCache | protected |
| frequency() const | Clocked | inline |
| getAddrRanges() const | BaseCache | inline |
| getBlockSize() const | BaseCache | inline |
| getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) | BaseCache | virtual |
| getProbeManager() | SimObject | |
| getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | BaseCache | virtual |
| hits | BaseCache | |
| inCache(Addr addr, bool is_secure) const =0 | BaseCache | pure virtual |
| incHitCount(PacketPtr pkt) | BaseCache | inline |
| incMissCount(PacketPtr pkt) | BaseCache | inline |
| init() | BaseCache | virtual |
| initState() | SimObject | virtual |
| inMissQueue(Addr addr, bool is_secure) const =0 | BaseCache | pure virtual |
| inRange(Addr addr) const | BaseCache | protected |
| isBlocked() const | BaseCache | inline |
| isDirty() const =0 | BaseCache | protectedpure virtual |
| isReadOnly | BaseCache | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lookupLatency | BaseCache | protected |
| markInService(MSHR *mshr, bool pending_modified_resp) | BaseCache | inlineprotected |
| markInService(WriteQueueEntry *entry) | BaseCache | inlineprotected |
| memInvalidate()=0 | BaseCache | protectedpure virtual |
| MemObject(const Params *params) | MemObject | |
| memSidePort | BaseCache | protected |
| memWriteback()=0 | BaseCache | protectedpure virtual |
| missCount | BaseCache | protected |
| misses | BaseCache | |
| missLatency | BaseCache | |
| missRate | BaseCache | |
| mshr_hits | BaseCache | |
| mshr_miss_latency | BaseCache | |
| mshr_misses | BaseCache | |
| mshr_uncacheable | BaseCache | |
| mshr_uncacheable_lat | BaseCache | |
| mshrMissRate | BaseCache | |
| mshrQueue | BaseCache | protected |
| MSHRQueue_MSHRs enum value | BaseCache | protected |
| MSHRQueue_WriteBuffer enum value | BaseCache | protected |
| MSHRQueueIndex enum name | BaseCache | protected |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| noTargetMSHR | BaseCache | protected |
| notifyFork() | Drainable | inlinevirtual |
| NUM_BLOCKED_CAUSES enum value | BaseCache | |
| numPwrStateTransitions | ClockedObject | protected |
| numTarget | BaseCache | protected |
| operator=(Clocked &)=delete | Clocked | protected |
| order | BaseCache | protected |
| overallAccesses | BaseCache | |
| overallAvgMissLatency | BaseCache | |
| overallAvgMshrMissLatency | BaseCache | |
| overallAvgMshrUncacheableLatency | BaseCache | |
| overallHits | BaseCache | |
| overallMisses | BaseCache | |
| overallMissLatency | BaseCache | |
| overallMissRate | BaseCache | |
| overallMshrHits | BaseCache | |
| overallMshrMisses | BaseCache | |
| overallMshrMissLatency | BaseCache | |
| overallMshrMissRate | BaseCache | |
| overallMshrUncacheable | BaseCache | |
| overallMshrUncacheableLatency | BaseCache | |
| params() const | MemObject | inline |
| Params typedef | MemObject | |
| prvEvalTick | ClockedObject | protected |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | BaseCache | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | SimObject | virtual |
| responseLatency | BaseCache | protected |
| schedMemSideSendEvent(Tick time) | BaseCache | inline |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setBlocked(BlockedCause cause) | BaseCache | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| startup() | SimObject | virtual |
| system | BaseCache | |
| ticksToCycles(Tick t) const | Clocked | inline |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| unusedPrefetches | BaseCache | |
| updateClockPeriod() const | Clocked | inline |
| voltage() const | Clocked | inline |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| writebacks | BaseCache | |
| writeBuffer | BaseCache | protected |
| ~BaseCache() | BaseCache | inline |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
