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DMASequencer Member List

This is the complete list of members for DMASequencer, including all inherited members.

_currPwrStateClockedObjectprotected
_paramsSimObjectprotected
ackCallback(const Addr &addr)DMASequencer
busy()DMASequencerinline
ckptCountSerializablestatic
ckptMaxCountSerializablestatic
ckptPrevCountSerializablestatic
Clocked(ClockDomain &clk_domain)Clockedinlineprotected
Clocked(Clocked &)=deleteClockedprotected
clockEdge(Cycles cycles=Cycles(0)) const Clockedinline
ClockedObject(const ClockedObjectParams *p)ClockedObject
clockPeriod() const Clockedinline
computeStats()ClockedObject
curCycle() const Clockedinline
currentSection()Serializablestatic
cyclesToTicks(Cycles c) const Clockedinline
dataCallback(const DataBlock &dblk, const Addr &addr)DMASequencer
deschedule(Event &event)EventManagerinline
deschedule(Event *event)EventManagerinline
descheduleDeadlockEvent() overrideDMASequencerinlinevirtual
DMASequencer(const Params *)DMASequencer
drain() overrideRubyPortvirtual
Drainable()Drainableprotected
drainResume()Drainableinlineprotectedvirtual
drainState() const Drainableinline
EventManager(EventManager &em)EventManagerinline
EventManager(EventManager *em)EventManagerinline
EventManager(EventQueue *eq)EventManagerinline
eventqEventManagerprotected
eventQueue() const EventManagerinline
find(const char *name)SimObjectstatic
frequency() const Clockedinline
getId()RubyPortinline
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) overrideRubyPortvirtual
getProbeManager()SimObject
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) overrideRubyPortvirtual
init() overrideDMASequencervirtual
initState()SimObjectvirtual
isCPUSequencer()RubyPortinline
isDeadlockEventScheduled() const overrideDMASequencerinlinevirtual
issueNext(const Addr &addr)DMASequencerprivate
loadState(CheckpointIn &cp)SimObjectvirtual
m_controllerRubyPortprotected
m_data_block_maskDMASequencerprivate
m_mandatory_q_ptrRubyPortprotected
m_max_outstanding_requestsDMASequencerprivate
m_outstanding_countDMASequencerprivate
m_RequestTableDMASequencerprivate
m_ruby_systemRubyPortprotected
m_usingRubyTesterRubyPortprotected
m_versionRubyPortprotected
makeRequest(PacketPtr pkt) overrideDMASequencervirtual
memInvalidate()SimObjectinlinevirtual
MemObject(const Params *params)MemObject
memWriteback()SimObjectinlinevirtual
name() const SimObjectinlinevirtual
nextCycle() const Clockedinline
notifyFork()Drainableinlinevirtual
numPwrStateTransitionsClockedObjectprotected
operator=(Clocked &)=deleteClockedprotected
outstandingCount() const overrideDMASequencerinlinevirtual
params() const MemObjectinline
Params typedefDMASequencer
prvEvalTickClockedObjectprotected
pwrState() const ClockedObjectinline
pwrState(Enums::PwrState)ClockedObject
pwrStateClkGateDistClockedObjectprotected
pwrStateName() const ClockedObjectinline
pwrStateResidencyTicksClockedObjectprotected
pwrStateWeights() const ClockedObject
recordRequestType(DMASequencerRequestType requestType)DMASequencer
recvTimingResp(PacketPtr pkt, PortID master_port_id)RubyPortprotected
regProbeListeners()SimObjectvirtual
regProbePoints()SimObjectvirtual
regStats() overrideClockedObjectvirtual
RequestTable typedefDMASequencerprivate
reschedule(Event &event, Tick when, bool always=false)EventManagerinline
reschedule(Event *event, Tick when, bool always=false)EventManagerinline
resetClock() const Clockedinlineprotected
resetStats()SimObjectvirtual
ruby_eviction_callback(Addr address)RubyPortprotected
ruby_hit_callback(PacketPtr pkt)RubyPortprotected
RubyPort(const Params *p)RubyPort
schedule(Event &event, Tick when)EventManagerinline
schedule(Event *event, Tick when)EventManagerinline
Serializable()Serializable
serialize(CheckpointOut &cp) const overrideClockedObjectvirtual
serializeAll(CheckpointOut &cp)SimObjectstatic
Serializable::serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) const Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const Serializableinline
setController(AbstractController *_cntrl)RubyPortinline
setCurTick(Tick newVal)EventManagerinline
signalDrainDone() const Drainableinlineprotected
SimObject(const Params *_params)SimObject
slave_portsRubyPortprotected
startup()SimObjectvirtual
systemRubyPortprotected
testDrainComplete()RubyPortprotected
ticksToCycles(Tick t) const Clockedinline
trySendRetries()RubyPortprotected
unserialize(CheckpointIn &cp) overrideClockedObjectvirtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
updateClockPeriod() const Clockedinline
voltage() const Clockedinline
wakeupEventQueue(Tick when=(Tick)-1)EventManagerinline
~Clocked()Clockedinlineprotectedvirtual
~Drainable()Drainableprotectedvirtual
~RubyPort()RubyPortinlinevirtual
~Serializable()Serializablevirtual
~SimObject()SimObjectvirtual

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