| _status | FullO3CPU< Impl > | |
| activateContext(ThreadID tid) override | FullO3CPU< Impl > | |
| activateStage(const StageIdx idx) | FullO3CPU< Impl > | inline |
| activateThread(ThreadID tid) | FullO3CPU< Impl > | |
| activeThreads | FullO3CPU< Impl > | protected |
| activityRec | FullO3CPU< Impl > | private |
| activityThisCycle() | FullO3CPU< Impl > | inline |
| addInst(DynInstPtr &inst) | FullO3CPU< Impl > | |
| BaseO3CPU(BaseCPUParams *params) | BaseO3CPU | |
| Blocked enum value | FullO3CPU< Impl > | |
| ccRegfileReads | FullO3CPU< Impl > | |
| ccRegfileWrites | FullO3CPU< Impl > | |
| checker | FullO3CPU< Impl > | |
| cleanUpRemovedInsts() | FullO3CPU< Impl > | |
| commit | FullO3CPU< Impl > | protected |
| commitDrained(ThreadID tid) | FullO3CPU< Impl > | |
| CommitIdx enum value | FullO3CPU< Impl > | |
| commitRenameMap | FullO3CPU< Impl > | protected |
| committedInsts | FullO3CPU< Impl > | |
| committedOps | FullO3CPU< Impl > | |
| cpi | FullO3CPU< Impl > | |
| CPUPolicy typedef | FullO3CPU< Impl > | |
| cpuWaitList | FullO3CPU< Impl > | |
| dcachePort | FullO3CPU< Impl > | protected |
| deactivateStage(const StageIdx idx) | FullO3CPU< Impl > | inline |
| deactivateThread(ThreadID tid) | FullO3CPU< Impl > | |
| decode | FullO3CPU< Impl > | protected |
| DecodeIdx enum value | FullO3CPU< Impl > | |
| decodeQueue | FullO3CPU< Impl > | |
| DecodeStruct typedef | FullO3CPU< Impl > | |
| demapDataPage(Addr vaddr, uint64_t asn) | FullO3CPU< Impl > | inline |
| demapInstPage(Addr vaddr, uint64_t asn) | FullO3CPU< Impl > | inline |
| demapPage(Addr vaddr, uint64_t asn) | FullO3CPU< Impl > | inline |
| drain() override | FullO3CPU< Impl > | |
| drainResume() override | FullO3CPU< Impl > | |
| drainSanityCheck() const | FullO3CPU< Impl > | private |
| dtb | FullO3CPU< Impl > | |
| dumpInsts() | FullO3CPU< Impl > | |
| DynInstPtr typedef | FullO3CPU< Impl > | |
| fetch | FullO3CPU< Impl > | protected |
| FetchIdx enum value | FullO3CPU< Impl > | |
| fetchQueue | FullO3CPU< Impl > | |
| FetchStruct typedef | FullO3CPU< Impl > | |
| fpRegfileReads | FullO3CPU< Impl > | |
| fpRegfileWrites | FullO3CPU< Impl > | |
| freeList | FullO3CPU< Impl > | protected |
| FullO3CPU(DerivO3CPUParams *params) | FullO3CPU< Impl > | |
| getAndIncrementInstSeq() | FullO3CPU< Impl > | inline |
| getDataPort() override | FullO3CPU< Impl > | inline |
| getFreeTid() | FullO3CPU< Impl > | |
| getInstPort() override | FullO3CPU< Impl > | inline |
| getInterrupts() | FullO3CPU< Impl > | |
| globalSeqNum | FullO3CPU< Impl > | |
| halt() | FullO3CPU< Impl > | inline |
| haltContext(ThreadID tid) override | FullO3CPU< Impl > | |
| Halted enum value | FullO3CPU< Impl > | |
| hwrei(ThreadID tid) | FullO3CPU< Impl > | |
| icachePort | FullO3CPU< Impl > | protected |
| Idle enum value | FullO3CPU< Impl > | |
| idleCycles | FullO3CPU< Impl > | |
| iew | FullO3CPU< Impl > | protected |
| IEWIdx enum value | FullO3CPU< Impl > | |
| iewQueue | FullO3CPU< Impl > | |
| IEWStruct typedef | FullO3CPU< Impl > | |
| ImplState typedef | FullO3CPU< Impl > | |
| init() override | FullO3CPU< Impl > | |
| insertThread(ThreadID tid) | FullO3CPU< Impl > | |
| instAddr(ThreadID tid) | FullO3CPU< Impl > | |
| instcount | FullO3CPU< Impl > | |
| instDone(ThreadID tid, DynInstPtr &inst) | FullO3CPU< Impl > | |
| instList | FullO3CPU< Impl > | |
| intRegfileReads | FullO3CPU< Impl > | |
| intRegfileWrites | FullO3CPU< Impl > | |
| ipc | FullO3CPU< Impl > | |
| isa | FullO3CPU< Impl > | protected |
| isDrained() const | FullO3CPU< Impl > | private |
| isDraining() const | FullO3CPU< Impl > | inline |
| itb | FullO3CPU< Impl > | |
| lastActivatedCycle | FullO3CPU< Impl > | |
| lastRunningCycle | FullO3CPU< Impl > | |
| ListIt typedef | FullO3CPU< Impl > | |
| microPC(ThreadID tid) | FullO3CPU< Impl > | |
| miscRegfileReads | FullO3CPU< Impl > | |
| miscRegfileWrites | FullO3CPU< Impl > | |
| nextInstAddr(ThreadID tid) | FullO3CPU< Impl > | |
| numActiveThreads() | FullO3CPU< Impl > | inline |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| NumStages enum value | FullO3CPU< Impl > | |
| O3CPU typedef | FullO3CPU< Impl > | |
| O3ThreadContext< Impl > class | FullO3CPU< Impl > | friend |
| pcState(const TheISA::PCState &newPCState, ThreadID tid) | FullO3CPU< Impl > | |
| pcState(ThreadID tid) | FullO3CPU< Impl > | |
| ppDataAccessComplete | FullO3CPU< Impl > | |
| ppInstAccessComplete | FullO3CPU< Impl > | |
| processInterrupts(const Fault &interrupt) | FullO3CPU< Impl > | |
| quiesceCycles | FullO3CPU< Impl > | |
| read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, int load_idx) | FullO3CPU< Impl > | inline |
| readArchCCReg(int reg_idx, ThreadID tid) | FullO3CPU< Impl > | |
| readArchFloatReg(int reg_idx, ThreadID tid) | FullO3CPU< Impl > | |
| readArchFloatRegInt(int reg_idx, ThreadID tid) | FullO3CPU< Impl > | |
| readArchIntReg(int reg_idx, ThreadID tid) | FullO3CPU< Impl > | |
| readCCReg(int reg_idx) | FullO3CPU< Impl > | |
| readFloatReg(int reg_idx) | FullO3CPU< Impl > | |
| readFloatRegBits(int reg_idx) | FullO3CPU< Impl > | |
| readIntReg(int reg_idx) | FullO3CPU< Impl > | |
| readMiscReg(int misc_reg, ThreadID tid) | FullO3CPU< Impl > | |
| readMiscRegNoEffect(int misc_reg, ThreadID tid) const | FullO3CPU< Impl > | |
| regFile | FullO3CPU< Impl > | protected |
| regProbePoints() override | FullO3CPU< Impl > | |
| regStats() override | FullO3CPU< Impl > | |
| removeFrontInst(DynInstPtr &inst) | FullO3CPU< Impl > | |
| removeInstsNotInROB(ThreadID tid) | FullO3CPU< Impl > | |
| removeInstsThisCycle | FullO3CPU< Impl > | |
| removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) | FullO3CPU< Impl > | |
| removeList | FullO3CPU< Impl > | |
| removeThread(ThreadID tid) | FullO3CPU< Impl > | |
| rename | FullO3CPU< Impl > | protected |
| RenameIdx enum value | FullO3CPU< Impl > | |
| renameMap | FullO3CPU< Impl > | protected |
| renameQueue | FullO3CPU< Impl > | |
| RenameStruct typedef | FullO3CPU< Impl > | |
| rob | FullO3CPU< Impl > | protected |
| Running enum value | FullO3CPU< Impl > | |
| scheduleTickEvent(Cycles delay) | FullO3CPU< Impl > | inlineprivate |
| scoreboard | FullO3CPU< Impl > | protected |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | FullO3CPU< Impl > | |
| setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid) | FullO3CPU< Impl > | |
| setArchFloatReg(int reg_idx, float val, ThreadID tid) | FullO3CPU< Impl > | |
| setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) | FullO3CPU< Impl > | |
| setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) | FullO3CPU< Impl > | |
| setCCReg(int reg_idx, TheISA::CCReg val) | FullO3CPU< Impl > | |
| setFloatReg(int reg_idx, TheISA::FloatReg val) | FullO3CPU< Impl > | |
| setFloatRegBits(int reg_idx, TheISA::FloatRegBits val) | FullO3CPU< Impl > | |
| setIntReg(int reg_idx, uint64_t val) | FullO3CPU< Impl > | |
| setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) | FullO3CPU< Impl > | |
| setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) | FullO3CPU< Impl > | |
| simPalCheck(int palFunc, ThreadID tid) | FullO3CPU< Impl > | |
| squashFromTC(ThreadID tid) | FullO3CPU< Impl > | |
| squashInstIt(const ListIt &instIt, ThreadID tid) | FullO3CPU< Impl > | inline |
| StageIdx enum name | FullO3CPU< Impl > | |
| startup() override | FullO3CPU< Impl > | |
| Status enum name | FullO3CPU< Impl > | |
| suspendContext(ThreadID tid) override | FullO3CPU< Impl > | |
| SwitchedOut enum value | FullO3CPU< Impl > | |
| switchOut() override | FullO3CPU< Impl > | |
| syscall(int64_t callnum, ThreadID tid, Fault *fault) | FullO3CPU< Impl > | |
| system | FullO3CPU< Impl > | |
| takeOverFrom(BaseCPU *oldCPU) override | FullO3CPU< Impl > | |
| tcBase(ThreadID tid) | FullO3CPU< Impl > | inline |
| Thread typedef | FullO3CPU< Impl > | |
| thread | FullO3CPU< Impl > | |
| threadMap | FullO3CPU< Impl > | |
| tick() | FullO3CPU< Impl > | |
| tickEvent | FullO3CPU< Impl > | private |
| tids | FullO3CPU< Impl > | |
| timeBuffer | FullO3CPU< Impl > | |
| timesIdled | FullO3CPU< Impl > | |
| TimeStruct typedef | FullO3CPU< Impl > | |
| totalCpi | FullO3CPU< Impl > | |
| totalInsts() const override | FullO3CPU< Impl > | |
| totalIpc | FullO3CPU< Impl > | |
| totalOps() const override | FullO3CPU< Impl > | |
| trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst) | FullO3CPU< Impl > | |
| tryDrain() | FullO3CPU< Impl > | private |
| unscheduleTickEvent() | FullO3CPU< Impl > | inlineprivate |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | FullO3CPU< Impl > | |
| updateThreadPriority() | FullO3CPU< Impl > | |
| verifyMemoryMode() const override | FullO3CPU< Impl > | |
| wakeCPU() | FullO3CPU< Impl > | |
| wakeup(ThreadID tid) override | FullO3CPU< Impl > | virtual |
| write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, uint8_t *data, int store_idx) | FullO3CPU< Impl > | inline |
| ~FullO3CPU() | FullO3CPU< Impl > | |
