_currPwrState | ClockedObject | protected |
_params | SimObject | protected |
BaseXBar(const BaseXBarParams *p) | BaseXBar | protected |
calcPacketTiming(PacketPtr pkt, Tick header_delay) | BaseXBar | protected |
checkPortCache(Addr addr) const | BaseXBar | inlineprotected |
ckptCount | Serializable | static |
ckptMaxCount | Serializable | static |
ckptPrevCount | Serializable | static |
clearPortCache() | BaseXBar | inlineprotected |
Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
Clocked(Clocked &)=delete | Clocked | protected |
clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
clockPeriod() const | Clocked | inline |
computeStats() | ClockedObject | |
curCycle() const | Clocked | inline |
currentSection() | Serializable | static |
cyclesToTicks(Cycles c) const | Clocked | inline |
defaultPortID | BaseXBar | protected |
defaultRange | BaseXBar | protected |
deschedule(Event &event) | EventManager | inline |
deschedule(Event *event) | EventManager | inline |
drain() override | SimObject | inlinevirtual |
Drainable() | Drainable | protected |
drainResume() | Drainable | inlineprotectedvirtual |
drainState() const | Drainable | inline |
EventManager(EventManager &em) | EventManager | inline |
EventManager(EventManager *em) | EventManager | inline |
EventManager(EventQueue *eq) | EventManager | inline |
eventq | EventManager | protected |
eventQueue() const | EventManager | inline |
find(const char *name) | SimObject | static |
findPort(Addr addr) | BaseXBar | protected |
forwardLatency | BaseXBar | protected |
frequency() const | Clocked | inline |
frontendLatency | BaseXBar | protected |
getAddrRanges() const | BaseXBar | protected |
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) | BaseXBar | virtual |
getProbeManager() | SimObject | |
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | BaseXBar | virtual |
gotAddrRanges | BaseXBar | protected |
gotAllAddrRanges | BaseXBar | protected |
HMCController(const HMCControllerParams *p) | HMCController | |
init() | BaseXBar | virtual |
initState() | SimObject | virtual |
loadState(CheckpointIn &cp) | SimObject | virtual |
masterPorts | BaseXBar | protected |
memInvalidate() | SimObject | inlinevirtual |
MemObject(const Params *params) | MemObject | |
memWriteback() | SimObject | inlinevirtual |
n_master_ports | HMCController | private |
name() const | SimObject | inlinevirtual |
nextCycle() const | Clocked | inline |
NoncoherentXBar(const NoncoherentXBarParams *p) | NoncoherentXBar | |
notifyFork() | Drainable | inlinevirtual |
numPwrStateTransitions | ClockedObject | protected |
operator=(Clocked &)=delete | Clocked | protected |
Params typedef | MemObject | |
params() const | MemObject | inline |
pktCount | BaseXBar | protected |
pktSize | BaseXBar | protected |
portCache | BaseXBar | protected |
portMap | BaseXBar | protected |
prvEvalTick | ClockedObject | protected |
pwrState() const | ClockedObject | inline |
pwrState(Enums::PwrState) | ClockedObject | |
pwrStateClkGateDist | ClockedObject | protected |
pwrStateName() const | ClockedObject | inline |
pwrStateResidencyTicks | ClockedObject | protected |
pwrStateWeights() const | ClockedObject | |
recvAtomic(PacketPtr pkt, PortID slave_port_id) | NoncoherentXBar | protected |
recvFunctional(PacketPtr pkt, PortID slave_port_id) | NoncoherentXBar | protected |
recvRangeChange(PortID master_port_id) | HMCController | privatevirtual |
recvReqRetry(PortID master_port_id) | NoncoherentXBar | protected |
recvTimingReq(PacketPtr pkt, PortID slave_port_id) | HMCController | privatevirtual |
recvTimingResp(PacketPtr pkt, PortID master_port_id) | NoncoherentXBar | protectedvirtual |
regProbeListeners() | SimObject | virtual |
regProbePoints() | SimObject | virtual |
regStats() | NoncoherentXBar | virtual |
reqLayers | NoncoherentXBar | protected |
reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
resetClock() const | Clocked | inlineprotected |
resetStats() | SimObject | virtual |
respLayers | NoncoherentXBar | protected |
responseLatency | BaseXBar | protected |
rotate_counter() | HMCController | private |
routeTo | BaseXBar | protected |
rr_counter | HMCController | private |
schedule(Event &event, Tick when) | EventManager | inline |
schedule(Event *event, Tick when) | EventManager | inline |
Serializable() | Serializable | |
serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
serializeAll(CheckpointOut &cp) | SimObject | static |
Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
setCurTick(Tick newVal) | EventManager | inline |
signalDrainDone() const | Drainable | inlineprotected |
SimObject(const Params *_params) | SimObject | |
slavePorts | BaseXBar | protected |
startup() | SimObject | virtual |
ticksToCycles(Tick t) const | Clocked | inline |
totPktSize | NoncoherentXBar | |
transDist | BaseXBar | protected |
unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
unserializeGlobals(CheckpointIn &cp) | Serializable | static |
unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
updateClockPeriod() const | Clocked | inline |
updatePortCache(short id, const AddrRange &range) | BaseXBar | inlineprotected |
useDefaultRange | BaseXBar | protected |
voltage() const | Clocked | inline |
wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
width | BaseXBar | protected |
xbarRanges | BaseXBar | protected |
~BaseXBar() | BaseXBar | virtual |
~Clocked() | Clocked | inlineprotectedvirtual |
~Drainable() | Drainable | protectedvirtual |
~NoncoherentXBar() | NoncoherentXBar | virtual |
~Serializable() | Serializable | virtual |
~SimObject() | SimObject | virtual |