gem5
|
This is the complete list of members for LTAGE, including all inherited members.
_params | SimObject | protected |
baseUpdate(Addr pc, bool taken, BranchInfo *bi) | LTAGE | private |
bindex(Addr pc_in) const | LTAGE | private |
BPredUnit(const Params *p) | BPredUnit | |
btable | LTAGE | private |
BTBLookup(Addr instPC) | BPredUnit | inline |
BTBUpdate(Addr instPC, const TheISA::PCState &target) | BPredUnit | inline |
btbUpdate(ThreadID tid, Addr branch_addr, void *&bp_history) override | LTAGE | virtual |
BTBValid(Addr instPC) | BPredUnit | inline |
ckptCount | Serializable | static |
ckptMaxCount | Serializable | static |
ckptPrevCount | Serializable | static |
ctrUpdate(int8_t &ctr, bool taken, int nbits) | LTAGE | private |
currentSection() | Serializable | static |
deschedule(Event &event) | EventManager | inline |
deschedule(Event *event) | EventManager | inline |
drain() override | SimObject | inlinevirtual |
Drainable() | Drainable | protected |
drainResume() | Drainable | inlineprotectedvirtual |
drainSanityCheck() const | BPredUnit | |
drainState() const | Drainable | inline |
dump() | BPredUnit | |
EventManager(EventManager &em) | EventManager | inline |
EventManager(EventManager *em) | EventManager | inline |
EventManager(EventQueue *eq) | EventManager | inline |
eventq | EventManager | protected |
eventQueue() const | EventManager | inline |
F(int phist, int size, int bank) const | LTAGE | private |
find(const char *name) | SimObject | static |
getBimodePred(Addr pc, BranchInfo *bi) const | LTAGE | private |
getGHR(ThreadID tid, void *bp_history) const override | LTAGE | virtual |
getLoop(Addr pc, BranchInfo *bi) const | LTAGE | private |
getProbeManager() | SimObject | |
gindex(ThreadID tid, Addr pc, int bank) const | LTAGE | inlineprivate |
gtable | LTAGE | private |
gtag(ThreadID tid, Addr pc, int bank) const | LTAGE | inlineprivate |
histBufferSize | LTAGE | private |
histLengths | LTAGE | private |
init() | SimObject | virtual |
initState() | SimObject | virtual |
instShiftAmt | BPredUnit | protected |
lindex(Addr pc_in) const | LTAGE | private |
loadState(CheckpointIn &cp) | SimObject | virtual |
logSizeBiMP | LTAGE | private |
logSizeLoopPred | LTAGE | private |
logSizeTagTables | LTAGE | private |
logTick | LTAGE | private |
lookup(ThreadID tid, Addr branch_addr, void *&bp_history) override | LTAGE | virtual |
loopUpdate(Addr pc, bool Taken, BranchInfo *bi) | LTAGE | private |
loopUseCounter | LTAGE | private |
ltable | LTAGE | private |
LTAGE(const LTAGEParams *params) | LTAGE | |
maxHist | LTAGE | private |
memInvalidate() | SimObject | inlinevirtual |
memWriteback() | SimObject | inlinevirtual |
minHist | LTAGE | private |
minTagWidth | LTAGE | private |
name() const | SimObject | inlinevirtual |
nHistoryTables | LTAGE | private |
notifyFork() | Drainable | inlinevirtual |
params() const | SimObject | inline |
Params typedef | BPredUnit | |
pmuProbePoint(const char *name) | BPredUnit | protected |
ppBranches | BPredUnit | protected |
ppMisses | BPredUnit | protected |
predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) | LTAGE | private |
BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid) | BPredUnit | |
regProbeListeners() | SimObject | virtual |
regProbePoints() override | BPredUnit | virtual |
regStats() override | BPredUnit | virtual |
reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
resetStats() | SimObject | virtual |
schedule(Event &event, Tick when) | EventManager | inline |
schedule(Event *event, Tick when) | EventManager | inline |
Serializable() | Serializable | |
serialize(CheckpointOut &cp) const override | SimObject | inlinevirtual |
serializeAll(CheckpointOut &cp) | SimObject | static |
Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
setCurTick(Tick newVal) | EventManager | inline |
signalDrainDone() const | Drainable | inlineprotected |
SimObject(const Params *_params) | SimObject | |
specLoopUpdate(Addr pc, bool taken, BranchInfo *bi) | LTAGE | private |
squash(ThreadID tid, void *bp_history) override | LTAGE | virtual |
squash(ThreadID tid, bool taken, void *bp_history) | LTAGE | private |
BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid) | BPredUnit | |
BPredUnit::squash(const InstSeqNum &squashed_sn, const TheISA::PCState &corr_target, bool actually_taken, ThreadID tid) | BPredUnit | |
startup() | SimObject | virtual |
tableIndices | LTAGE | private |
tableTags | LTAGE | private |
tagTableCounterBits | LTAGE | private |
tagTableSizes | LTAGE | private |
tagWidths | LTAGE | private |
tCounter | LTAGE | private |
threadHistory | LTAGE | private |
uncondBranch(ThreadID tid, Addr br_pc, void *&bp_history) override | LTAGE | virtual |
unserialize(CheckpointIn &cp) override | SimObject | inlinevirtual |
unserializeGlobals(CheckpointIn &cp) | Serializable | static |
unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed) override | LTAGE | virtual |
update(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *bi) | LTAGE | private |
BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid) | BPredUnit | |
updateGHist(uint8_t *&h, bool dir, uint8_t *tab, int &PT) | LTAGE | private |
updateHistories(ThreadID tid, Addr branch_pc, bool taken, void *b) | LTAGE | private |
useAltPredForNewlyAllocated | LTAGE | private |
wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
~Drainable() | Drainable | protectedvirtual |
~Serializable() | Serializable | virtual |
~SimObject() | SimObject | virtual |