| _currPwrState | ClockedObject | protected |
| _params | SimObject | protected |
| AddrPriority typedef | QueuedPrefetcher | protected |
| BasePrefetcher(const BasePrefetcherParams *p) | BasePrefetcher | |
| blkSize | BasePrefetcher | protected |
| blockAddress(Addr a) const | BasePrefetcher | protected |
| blockIndex(Addr a) const | BasePrefetcher | protected |
| cache | BasePrefetcher | protected |
| cacheSnoop | QueuedPrefetcher | protected |
| calculatePrefetch(const PacketPtr &pkt, std::vector< AddrPriority > &addresses) | StridePrefetcher | virtual |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| computeStats() | ClockedObject | |
| const_iterator typedef | QueuedPrefetcher | protected |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| degree | StridePrefetcher | protected |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| find(const char *name) | SimObject | static |
| frequency() const | Clocked | inline |
| getPacket() | QueuedPrefetcher | virtual |
| getProbeManager() | SimObject | |
| inCache(Addr addr, bool is_secure) const | BasePrefetcher | protected |
| init() | SimObject | virtual |
| initState() | SimObject | virtual |
| inMissQueue(Addr addr, bool is_secure) const | BasePrefetcher | protected |
| inPrefetch(Addr address, bool is_secure) const | QueuedPrefetcher | protected |
| inPrefetch(Addr address, bool is_secure) | QueuedPrefetcher | protected |
| insert(AddrPriority &info, bool is_secure) | QueuedPrefetcher | |
| iterator typedef | QueuedPrefetcher | protected |
| latency | QueuedPrefetcher | protected |
| lBlkSize | BasePrefetcher | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| masterId | BasePrefetcher | protected |
| maxConf | StridePrefetcher | protected |
| memInvalidate() | SimObject | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| minConf | StridePrefetcher | protected |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| nextPrefetchReadyTime() const | QueuedPrefetcher | inlinevirtual |
| notify(const PacketPtr &pkt) | QueuedPrefetcher | virtual |
| notifyFork() | Drainable | inlinevirtual |
| numPwrStateTransitions | ClockedObject | protected |
| observeAccess(const PacketPtr &pkt) const | BasePrefetcher | protected |
| onData | BasePrefetcher | protected |
| onInst | BasePrefetcher | protected |
| onMiss | BasePrefetcher | protected |
| onRead | BasePrefetcher | protected |
| onWrite | BasePrefetcher | protected |
| operator=(Clocked &)=delete | Clocked | protected |
| pageAddress(Addr a) const | BasePrefetcher | protected |
| pageBytes | BasePrefetcher | protected |
| pageIthBlockAddress(Addr page, uint32_t i) const | BasePrefetcher | protected |
| pageOffset(Addr a) const | BasePrefetcher | protected |
| params() const | ClockedObject | inline |
| Params typedef | ClockedObject | |
| pcHash(Addr pc) const | StridePrefetcher | inlineprotected |
| pcTable | StridePrefetcher | protected |
| pcTableAssoc | StridePrefetcher | protected |
| pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry *&entry) | StridePrefetcher | inlineprotected |
| pcTableSets | StridePrefetcher | protected |
| pcTableVictim(Addr pc, int master_id) | StridePrefetcher | inlineprotected |
| pfBufferHit | QueuedPrefetcher | protected |
| pfIdentified | QueuedPrefetcher | protected |
| pfInCache | QueuedPrefetcher | protected |
| pfIssued | BasePrefetcher | protected |
| pfq | QueuedPrefetcher | protected |
| pfRemovedFull | QueuedPrefetcher | protected |
| pfSpanPage | QueuedPrefetcher | protected |
| prvEvalTick | ClockedObject | protected |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| QueuedPrefetcher(const QueuedPrefetcherParams *p) | QueuedPrefetcher | |
| queueFilter | QueuedPrefetcher | protected |
| queueSize | QueuedPrefetcher | protected |
| queueSquash | QueuedPrefetcher | protected |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | QueuedPrefetcher | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | SimObject | virtual |
| samePage(Addr a, Addr b) const | BasePrefetcher | protected |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCache(BaseCache *_cache) | BasePrefetcher | |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| startConf | StridePrefetcher | protected |
| startup() | SimObject | virtual |
| StridePrefetcher(const StridePrefetcherParams *p) | StridePrefetcher | |
| system | BasePrefetcher | protected |
| tagPrefetch | QueuedPrefetcher | protected |
| threshConf | StridePrefetcher | protected |
| ticksToCycles(Tick t) const | Clocked | inline |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateClockPeriod() const | Clocked | inline |
| useMasterId | StridePrefetcher | protected |
| voltage() const | Clocked | inline |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| ~BasePrefetcher() | BasePrefetcher | inlinevirtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~QueuedPrefetcher() | QueuedPrefetcher | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
