| _status | BaseSimpleCPU | protected |
| activateContext(ThreadID thread_num) override | TimingSimpleCPU | |
| activeThreads | BaseSimpleCPU | |
| advanceInst(const Fault &fault) | TimingSimpleCPU | |
| advancePC(const Fault &fault) | BaseSimpleCPU | |
| BaseSimpleCPU(BaseSimpleCPUParams *params) | BaseSimpleCPU | |
| branchPred | BaseSimpleCPU | protected |
| buildPacket(RequestPtr req, bool read) | TimingSimpleCPU | private |
| buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr req1, RequestPtr req2, RequestPtr req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| checker | BaseSimpleCPU | |
| checkForInterrupts() | BaseSimpleCPU | |
| checkPcEventQueue() | BaseSimpleCPU | protected |
| completeDataAccess(PacketPtr pkt) | TimingSimpleCPU | |
| completeIfetch(PacketPtr) | TimingSimpleCPU | |
| countInst() | BaseSimpleCPU | |
| curMacroStaticInst | BaseSimpleCPU | |
| curStaticInst | BaseSimpleCPU | |
| curThread | BaseSimpleCPU | protected |
| dbg_vtophys(Addr addr) | BaseSimpleCPU | |
| dcache_pkt | TimingSimpleCPU | private |
| dcachePort | TimingSimpleCPU | private |
| DcacheRetry enum value | BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| drain() override | TimingSimpleCPU | |
| drainResume() override | TimingSimpleCPU | |
| DTBWaitResponse enum value | BaseSimpleCPU | protected |
| Faulting enum value | BaseSimpleCPU | protected |
| fetch() | TimingSimpleCPU | |
| FetchEvent typedef | TimingSimpleCPU | private |
| fetchEvent | TimingSimpleCPU | private |
| fetchTranslation | TimingSimpleCPU | private |
| finishTranslation(WholeTranslationState *state) | TimingSimpleCPU | |
| getDataPort() override | TimingSimpleCPU | inlineprotected |
| getInstPort() override | TimingSimpleCPU | inlineprotected |
| haltContext(ThreadID thread_num) override | BaseSimpleCPU | |
| handleReadPacket(PacketPtr pkt) | TimingSimpleCPU | private |
| handleWritePacket() | TimingSimpleCPU | private |
| icachePort | TimingSimpleCPU | private |
| IcacheRetry enum value | BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| Idle enum value | BaseSimpleCPU | protected |
| ifetch_pkt | TimingSimpleCPU | private |
| init() override | TimingSimpleCPU | |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags) override | TimingSimpleCPU | virtual |
| inst | BaseSimpleCPU | |
| isDrained() | TimingSimpleCPU | inlineprivate |
| isSquashed() const | TimingSimpleCPU | inline |
| ITBWaitResponse enum value | BaseSimpleCPU | protected |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| postExecute() | BaseSimpleCPU | |
| preExecute() | BaseSimpleCPU | |
| previousCycle | TimingSimpleCPU | private |
| printAddr(Addr a) | TimingSimpleCPU | |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags) override | TimingSimpleCPU | virtual |
| regStats() override | BaseSimpleCPU | |
| resetStats() override | BaseSimpleCPU | |
| Running enum value | BaseSimpleCPU | protected |
| sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read) | TimingSimpleCPU | private |
| sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc) | TimingSimpleCPU | |
| sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | BaseSimpleCPU | |
| setupFetchRequest(Request *req) | BaseSimpleCPU | |
| startup() override | BaseSimpleCPU | |
| Status enum name | BaseSimpleCPU | protected |
| suspendContext(ThreadID thread_num) override | TimingSimpleCPU | |
| swapActiveThread() | BaseSimpleCPU | protected |
| switchOut() override | TimingSimpleCPU | |
| takeOverFrom(BaseCPU *oldCPU) override | TimingSimpleCPU | |
| threadInfo | BaseSimpleCPU | |
| threadSnoop(PacketPtr pkt, ThreadID sender) | TimingSimpleCPU | private |
| TimingSimpleCPU(TimingSimpleCPUParams *params) | TimingSimpleCPU | |
| totalInsts() const override | BaseSimpleCPU | |
| totalOps() const override | BaseSimpleCPU | |
| traceData | BaseSimpleCPU | |
| translationFault(const Fault &fault) | TimingSimpleCPU | private |
| tryCompleteDrain() | TimingSimpleCPU | private |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | BaseSimpleCPU | |
| updateCycleCounts() | TimingSimpleCPU | private |
| verifyMemoryMode() const override | TimingSimpleCPU | |
| wakeup(ThreadID tid) override | BaseSimpleCPU | |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) override | TimingSimpleCPU | virtual |
| ~BaseSimpleCPU() | BaseSimpleCPU | virtual |
| ~TimingSimpleCPU() | TimingSimpleCPU | virtual |
