_currPwrState | ClockedObject | protected |
_params | SimObject | protected |
activeDoorbells | UFSHostDevice | private |
cacheBlockSize() const | DmaDevice | inline |
checkDrain() | UFSHostDevice | |
ckptCount | Serializable | static |
ckptMaxCount | Serializable | static |
ckptPrevCount | Serializable | static |
clearInterrupt() | UFSHostDevice | private |
Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
Clocked(Clocked &)=delete | Clocked | protected |
clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
clockPeriod() const | Clocked | inline |
commandHandler() | UFSHostDevice | private |
computeStats() | ClockedObject | |
countInt | UFSHostDevice | private |
curCycle() const | Clocked | inline |
currentSection() | Serializable | static |
cyclesToTicks(Cycles c) const | Clocked | inline |
deschedule(Event &event) | EventManager | inline |
deschedule(Event *event) | EventManager | inline |
DmaDevice(const Params *p) | DmaDevice | |
dmaPending() const | DmaDevice | inline |
dmaPort | DmaDevice | protected |
dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | DmaDevice | inline |
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | DmaDevice | inline |
dmaWriteInfo | UFSHostDevice | private |
drain() override | UFSHostDevice | virtual |
Drainable() | Drainable | protected |
drainResume() | Drainable | inlineprotectedvirtual |
drainState() const | Drainable | inline |
EventManager(EventManager &em) | EventManager | inline |
EventManager(EventManager *em) | EventManager | inline |
EventManager(EventQueue *eq) | EventManager | inline |
eventq | EventManager | protected |
eventQueue() const | EventManager | inline |
finalUTP() | UFSHostDevice | private |
find(const char *name) | SimObject | static |
frequency() const | Clocked | inline |
garbage | UFSHostDevice | private |
generateInterrupt() | UFSHostDevice | private |
getAddrRanges() const override | UFSHostDevice | privatevirtual |
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) override | DmaDevice | virtual |
getProbeManager() | SimObject | |
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | PioDevice | virtual |
gic | UFSHostDevice | private |
idlePhaseStart | UFSHostDevice | private |
init() override | DmaDevice | virtual |
initState() | SimObject | virtual |
intNum | UFSHostDevice | private |
loadState(CheckpointIn &cp) | SimObject | virtual |
lunAvail | UFSHostDevice | private |
LUNSignal() | UFSHostDevice | private |
manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t offset, uint32_t sg_table_length, struct UFSHCDSGEntry *sglist) | UFSHostDevice | private |
manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t sg_table_length, struct UFSHCDSGEntry *sglist) | UFSHostDevice | private |
memInvalidate() | SimObject | inlinevirtual |
MemObject(const Params *params) | MemObject | |
memReadCallback | UFSHostDevice | private |
memWriteback() | SimObject | inlinevirtual |
name() const | SimObject | inlinevirtual |
nextCycle() const | Clocked | inline |
notifyFork() | Drainable | inlinevirtual |
numPwrStateTransitions | ClockedObject | protected |
operator=(Clocked &)=delete | Clocked | protected |
Params typedef | DmaDevice | |
params() const | PioDevice | inline |
pendingDoorbells | UFSHostDevice | private |
pioAddr | UFSHostDevice | private |
pioDelay | UFSHostDevice | private |
PioDevice(const Params *p) | PioDevice | |
pioPort | PioDevice | protected |
pioSize | UFSHostDevice | private |
prvEvalTick | ClockedObject | protected |
pwrState() const | ClockedObject | inline |
pwrState(Enums::PwrState) | ClockedObject | |
pwrStateClkGateDist | ClockedObject | protected |
pwrStateName() const | ClockedObject | inline |
pwrStateResidencyTicks | ClockedObject | protected |
pwrStateWeights() const | ClockedObject | |
read(PacketPtr pkt) override | UFSHostDevice | privatevirtual |
readCallback() | UFSHostDevice | private |
readDevice(bool lastTransfer, Addr SCSIStart, uint32_t SCSISize, uint8_t *SCSIDestination, bool no_cache, Event *additional_action) | UFSHostDevice | private |
readDone() | UFSHostDevice | private |
readDoneEvent | UFSHostDevice | private |
readGarbage() | UFSHostDevice | private |
readGarbageEventQueue | UFSHostDevice | private |
readPendingNum | UFSHostDevice | private |
regControllerCapabilities enum value | UFSHostDevice | private |
regControllerDEVID enum value | UFSHostDevice | private |
regControllerEnable enum value | UFSHostDevice | private |
regControllerPRODID enum value | UFSHostDevice | private |
regControllerStatus enum value | UFSHostDevice | private |
regInterruptEnable enum value | UFSHostDevice | private |
regInterruptStatus enum value | UFSHostDevice | private |
regProbeListeners() | SimObject | virtual |
regProbePoints() | SimObject | virtual |
regStats() override | UFSHostDevice | privatevirtual |
regUFSVersion enum value | UFSHostDevice | private |
regUICCommand enum value | UFSHostDevice | private |
regUICCommandArg1 enum value | UFSHostDevice | private |
regUICCommandArg2 enum value | UFSHostDevice | private |
regUICCommandArg3 enum value | UFSHostDevice | private |
regUICErrorCodeDataLinkLayer enum value | UFSHostDevice | private |
regUICErrorCodeDME enum value | UFSHostDevice | private |
regUICErrorCodeNetworkLayer enum value | UFSHostDevice | private |
regUICErrorCodePHYAdapterLayer enum value | UFSHostDevice | private |
regUICErrorCodeTransportLayer enum value | UFSHostDevice | private |
regUTPTaskREQDoorbell enum value | UFSHostDevice | private |
regUTPTaskREQListBaseH enum value | UFSHostDevice | private |
regUTPTaskREQListBaseL enum value | UFSHostDevice | private |
regUTPTaskREQListClear enum value | UFSHostDevice | private |
regUTPTaskREQListRunStop enum value | UFSHostDevice | private |
regUTPTransferREQDoorbell enum value | UFSHostDevice | private |
regUTPTransferREQINTAGGControl enum value | UFSHostDevice | private |
regUTPTransferREQListBaseH enum value | UFSHostDevice | private |
regUTPTransferREQListBaseL enum value | UFSHostDevice | private |
regUTPTransferREQListClear enum value | UFSHostDevice | private |
regUTPTransferREQListRunStop enum value | UFSHostDevice | private |
request_out_datain | UFSHostDevice | private |
requestHandler() | UFSHostDevice | private |
reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
resetClock() const | Clocked | inlineprotected |
resetStats() | SimObject | virtual |
schedule(Event &event, Tick when) | EventManager | inline |
schedule(Event *event, Tick when) | EventManager | inline |
SCSIInfo | UFSHostDevice | private |
SCSIResume(uint32_t lun_id) | UFSHostDevice | private |
SCSIResumeEvent | UFSHostDevice | private |
SCSIStart() | UFSHostDevice | private |
Serializable() | Serializable | |
serialize(CheckpointOut &cp) const override | UFSHostDevice | virtual |
serializeAll(CheckpointOut &cp) | SimObject | static |
Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
setCurTick(Tick newVal) | EventManager | inline |
setValues() | UFSHostDevice | private |
signalDrainDone() const | Drainable | inlineprotected |
SimObject(const Params *_params) | SimObject | |
SSDReadPending | UFSHostDevice | private |
SSDWriteinfo | UFSHostDevice | private |
startup() | SimObject | virtual |
stats | UFSHostDevice | private |
sys | PioDevice | protected |
taskCommandTrack | UFSHostDevice | private |
taskEventQueue | UFSHostDevice | private |
taskHandler(struct UTPUPIUTaskReq *request_in, uint32_t req_pos, Addr finaladdress, uint32_t finalsize) | UFSHostDevice | private |
taskInfo | UFSHostDevice | private |
taskStart() | UFSHostDevice | private |
ticksToCycles(Tick t) const | Clocked | inline |
transactionStart | UFSHostDevice | private |
transferDone(Addr responseStartAddr, uint32_t req_pos, struct UTPUPIURSP request_out, uint32_t size, Addr address, uint8_t *destination, bool finished, uint32_t lun_id) | UFSHostDevice | private |
transferDoneCallback | UFSHostDevice | private |
transferEnd | UFSHostDevice | private |
transferEventQueue | UFSHostDevice | private |
transferHandler(struct UTPTransferReqDesc *request_in, int req_pos, Addr finaladdress, uint32_t finalsize, uint32_t done) | UFSHostDevice | private |
transferStart() | UFSHostDevice | private |
transferStartInfo | UFSHostDevice | private |
transferTrack | UFSHostDevice | private |
UFSDevice | UFSHostDevice | private |
UFSHCIMem | UFSHostDevice | private |
UFSHCIRegisters enum name | UFSHostDevice | private |
UFSHostDevice(const UFSHostDeviceParams *p) | UFSHostDevice | |
UFSSlots | UFSHostDevice | private |
UICCommandCOMPL | UFSHostDevice | privatestatic |
UICCommandReady | UFSHostDevice | privatestatic |
unserialize(CheckpointIn &cp) override | UFSHostDevice | virtual |
unserializeGlobals(CheckpointIn &cp) | Serializable | static |
unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
updateClockPeriod() const | Clocked | inline |
UTPEvent | UFSHostDevice | private |
UTPTaskREQCOMPL | UFSHostDevice | privatestatic |
UTPTransferREQCOMPL | UFSHostDevice | privatestatic |
voltage() const | Clocked | inline |
wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
write(PacketPtr pkt) override | UFSHostDevice | privatevirtual |
writeDevice(Event *additional_action, bool toDisk, Addr start, int size, uint8_t *destination, uint64_t SCSIDiskOffset, uint32_t lun_id) | UFSHostDevice | private |
writeDone() | UFSHostDevice | private |
writeDoneEvent | UFSHostDevice | private |
writePendingNum | UFSHostDevice | private |
~Clocked() | Clocked | inlineprotectedvirtual |
~DmaDevice() | DmaDevice | inlinevirtual |
~Drainable() | Drainable | protectedvirtual |
~PioDevice() | PioDevice | virtual |
~Serializable() | Serializable | virtual |
~SimObject() | SimObject | virtual |