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fetch2.hh
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39 
47 #ifndef __CPU_MINOR_FETCH2_HH__
48 #define __CPU_MINOR_FETCH2_HH__
49 
50 #include "cpu/minor/buffers.hh"
51 #include "cpu/minor/cpu.hh"
52 #include "cpu/minor/pipe_data.hh"
53 #include "cpu/pred/bpred_unit.hh"
54 #include "params/MinorCPU.hh"
55 
56 namespace Minor
57 {
58 
61 class Fetch2 : public Named
62 {
63  protected:
66 
69 
73 
76 
79 
82 
84  unsigned int outputWidth;
85 
89 
92 
93  public:
94  /* Public so that Pipeline can pass it to Fetch1 */
96 
97  protected:
101 
104  inputIndex(0),
105  pc(TheISA::PCState(0)),
106  havePC(false),
107  lastStreamSeqNum(InstId::firstStreamSeqNum),
108  fetchSeqNum(InstId::firstFetchSeqNum),
109  expectedStreamSeqNum(InstId::firstStreamSeqNum),
110  predictionSeqNum(InstId::firstPredictionSeqNum),
111  blocked(false)
112  { }
113 
115  inputIndex(other.inputIndex),
116  pc(other.pc),
117  havePC(other.havePC),
121  blocked(other.blocked)
122  { }
123 
126  unsigned int inputIndex;
127 
128 
136 
140  bool havePC;
141 
145 
149 
155 
160 
162  bool blocked;
163  };
164 
167 
168  protected:
171  const ForwardLineData *getInput(ThreadID tid);
172 
174  void popInput(ThreadID tid);
175 
178  void dumpAllInput(ThreadID tid);
179 
182  void updateBranchPrediction(const BranchData &branch);
183 
187  void predictBranch(MinorDynInstPtr inst, BranchData &branch);
188 
192 
193  public:
194  Fetch2(const std::string &name,
195  MinorCPU &cpu_,
196  MinorCPUParams &params,
198  Latch<BranchData>::Output branchInp_,
199  Latch<BranchData>::Input predictionOut_,
201  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
202 
203  public:
205  void evaluate();
206 
207  void minorTrace() const;
208 
212  bool isDrained();
213 };
214 
215 }
216 
217 #endif /* __CPU_MINOR_FETCH2_HH__ */
InstSeqNum fetchSeqNum
Fetch2 is the source of fetch sequence numbers.
Definition: fetch2.hh:148
Latch< BranchData >::Output branchInp
Input port carrying branches from Execute.
Definition: fetch2.hh:72
const std::string & name() const
Definition: trace.hh:149
Top level definition of the Minor in-order CPU model.
Latch< ForwardInstData >::Input out
Output port carrying instructions into Decode.
Definition: fetch2.hh:78
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: fetch2.hh:88
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty...
Definition: buffers.hh:563
std::vector< InputBuffer< ForwardLineData > > inputBuffer
Definition: fetch2.hh:95
Line fetch data in the forward direction.
Definition: pipe_data.hh:173
TheISA::PCState pc
Remembered program counter value.
Definition: fetch2.hh:135
std::vector< Fetch2ThreadInfo > fetchInfo
Definition: fetch2.hh:165
Latch< BranchData >::Input predictionOut
Output port carrying predictions back to Fetch1.
Definition: fetch2.hh:75
Id for lines and instructions.
Definition: dyn_inst.hh:70
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: fetch2.hh:84
STL vector class.
Definition: stl.hh:40
Definition: trace.hh:140
ThreadID threadPriority
Definition: fetch2.hh:166
This stage receives lines of data from Fetch1, separates them into instructions and passes them to De...
Definition: fetch2.hh:61
bool isDrained()
Is this stage drained? For Fetch2, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: fetch2.cc:585
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: fetch2.hh:65
InstSeqNum predictionSeqNum
Fetch2 is the source of prediction sequence numbers.
Definition: fetch2.hh:159
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: fetch2.cc:105
uint64_t InstSeqNum
Definition: inst_seq.hh:40
Classes for buffer, queue and FIFO behaviour.
void predictBranch(MinorDynInstPtr inst, BranchData &branch)
Predicts branches for the given instruction.
Definition: fetch2.cc:188
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:67
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
unsigned int inputIndex
Index into an incompletely processed input line that instructions are to be extracted from...
Definition: fetch2.hh:126
InstSeqNum lastStreamSeqNum
Stream sequence number of the last seen line used to identify changes of instruction stream...
Definition: fetch2.hh:144
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:64
Fetch2ThreadInfo(const Fetch2ThreadInfo &other)
Definition: fetch2.hh:114
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch2.cc:555
Fetch2ThreadInfo()
Default constructor.
Definition: fetch2.hh:103
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
void dumpAllInput(ThreadID tid)
Dump the whole contents of the input buffer.
Definition: fetch2.cc:116
InstSeqNum expectedStreamSeqNum
Stream sequence number remembered from last time the predictionSeqNum changed.
Definition: fetch2.hh:154
Data members after this line are cycle-to-cycle state.
Definition: fetch2.hh:100
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch2.hh:81
Latch< ForwardLineData >::Output inp
Input port carrying lines from Fetch1.
Definition: fetch2.hh:68
BPredUnit & branchPredictor
Branch predictor passed from Python configuration.
Definition: fetch2.hh:91
Fetch2(const std::string &name, MinorCPU &cpu_, MinorCPUParams &params, Latch< ForwardLineData >::Output inp_, Latch< BranchData >::Output branchInp_, Latch< BranchData >::Input predictionOut_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: fetch2.cc:55
void updateBranchPrediction(const BranchData &branch)
Update local branch prediction structures from feedback from Execute.
Definition: fetch2.cc:126
const ForwardLineData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition: fetch2.cc:94
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:243
bool blocked
Blocked indication for report.
Definition: fetch2.hh:162
bool havePC
PC is currently valid.
Definition: fetch2.hh:140
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch2.cc:239
void minorTrace() const
Definition: fetch2.cc:597

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