47 #ifndef __CPU_MINOR_FETCH2_HH__
48 #define __CPU_MINOR_FETCH2_HH__
54 #include "params/MinorCPU.hh"
196 MinorCPUParams ¶ms,
InstSeqNum fetchSeqNum
Fetch2 is the source of fetch sequence numbers.
Latch< BranchData >::Output branchInp
Input port carrying branches from Execute.
const std::string & name() const
Top level definition of the Minor in-order CPU model.
Latch< ForwardInstData >::Input out
Output port carrying instructions into Decode.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
std::vector< InputBuffer< ForwardLineData > > inputBuffer
Line fetch data in the forward direction.
TheISA::PCState pc
Remembered program counter value.
std::vector< Fetch2ThreadInfo > fetchInfo
Latch< BranchData >::Input predictionOut
Output port carrying predictions back to Fetch1.
Id for lines and instructions.
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
This stage receives lines of data from Fetch1, separates them into instructions and passes them to De...
bool isDrained()
Is this stage drained? For Fetch2, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
MinorCPU & cpu
Pointer back to the containing CPU.
InstSeqNum predictionSeqNum
Fetch2 is the source of prediction sequence numbers.
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Classes for buffer, queue and FIFO behaviour.
void predictBranch(MinorDynInstPtr inst, BranchData &branch)
Predicts branches for the given instruction.
Basically a wrapper class to hold both the branch predictor and the BTB.
int16_t ThreadID
Thread index/ID type.
unsigned int inputIndex
Index into an incompletely processed input line that instructions are to be extracted from...
InstSeqNum lastStreamSeqNum
Stream sequence number of the last seen line used to identify changes of instruction stream...
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Fetch2ThreadInfo(const Fetch2ThreadInfo &other)
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Fetch2ThreadInfo()
Default constructor.
GenericISA::SimplePCState< MachInst > PCState
void dumpAllInput(ThreadID tid)
Dump the whole contents of the input buffer.
InstSeqNum expectedStreamSeqNum
Stream sequence number remembered from last time the predictionSeqNum changed.
Data members after this line are cycle-to-cycle state.
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Latch< ForwardLineData >::Output inp
Input port carrying lines from Fetch1.
BPredUnit & branchPredictor
Branch predictor passed from Python configuration.
Fetch2(const std::string &name, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< ForwardLineData >::Output inp_, Latch< BranchData >::Output branchInp_, Latch< BranchData >::Input predictionOut_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
void updateBranchPrediction(const BranchData &branch)
Update local branch prediction structures from feedback from Execute.
const ForwardLineData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
bool blocked
Blocked indication for report.
bool havePC
PC is currently valid.
void evaluate()
Pass on input/buffer data to the output if you can.