bpred_unit.hh

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/*
 * Copyright (c) 2011-2012, 2014 ARM Limited
 * Copyright (c) 2010 The University of Edinburgh
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *
 * Authors: Kevin Lim
 *          Korey Sewell
 *          Timothy M. Jones
 *          Nilay Vaish
 */

#ifndef __CPU_PRED_BPRED_UNIT_HH__
#define __CPU_PRED_BPRED_UNIT_HH__

#include <deque>

#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/pred/btb.hh"
#include "cpu/pred/indirect.hh"
#include "cpu/pred/ras.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "params/BranchPredictor.hh"
#include "sim/probe/pmu.hh"
#include "sim/sim_object.hh"

class BPredUnit : public SimObject
{
  public:
      typedef BranchPredictorParams Params;
    BPredUnit(const Params *p);

    void regStats() override;

    void regProbePoints() override;

    void drainSanityCheck() const;

    bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
                 TheISA::PCState &pc, ThreadID tid);

    // @todo: Rename this function.
    virtual void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) = 0;

    void update(const InstSeqNum &done_sn, ThreadID tid);

    void squash(const InstSeqNum &squashed_sn, ThreadID tid);

    void squash(const InstSeqNum &squashed_sn,
                const TheISA::PCState &corr_target,
                bool actually_taken, ThreadID tid);

    virtual void squash(ThreadID tid, void *bp_history) = 0;

    virtual bool lookup(ThreadID tid, Addr instPC, void * &bp_history) = 0;

    virtual void btbUpdate(ThreadID tid, Addr instPC, void * &bp_history) = 0;

    bool BTBValid(Addr instPC)
    { return BTB.valid(instPC, 0); }

    TheISA::PCState BTBLookup(Addr instPC)
    { return BTB.lookup(instPC, 0); }

    virtual void update(ThreadID tid, Addr instPC, bool taken,
                        void *bp_history, bool squashed) = 0;
    void BTBUpdate(Addr instPC, const TheISA::PCState &target)
    { BTB.update(instPC, target, 0); }


    virtual unsigned getGHR(ThreadID tid, void* bp_history) const { return 0; }

    void dump();

  private:
    struct PredictorHistory {
        PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
                         bool pred_taken, void *bp_history,
                         ThreadID _tid)
            : seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0),
              RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0),
              wasCall(0), wasReturn(0), wasIndirect(0)
        {}

        bool operator==(const PredictorHistory &entry) const {
            return this->seqNum == entry.seqNum;
        }

        InstSeqNum seqNum;

        Addr pc;

        void *bpHistory;

        TheISA::PCState RASTarget;

        unsigned RASIndex;

        ThreadID tid;

        bool predTaken;

        bool usedRAS;

        /* Whether or not the RAS was pushed */
        bool pushedRAS;

        bool wasCall;

        bool wasReturn;

        bool wasIndirect;
    };

    typedef std::deque<PredictorHistory> History;

    const unsigned numThreads;


    std::vector<History> predHist;

    DefaultBTB BTB;

    std::vector<ReturnAddrStack> RAS;

    const bool useIndirect;

    IndirectPredictor iPred;

    Stats::Scalar lookups;
    Stats::Scalar condPredicted;
    Stats::Scalar condIncorrect;
    Stats::Scalar BTBLookups;
    Stats::Scalar BTBHits;
    Stats::Scalar BTBCorrect;
    Stats::Formula BTBHitPct;
    Stats::Scalar usedRAS;
    Stats::Scalar RASIncorrect;

    Stats::Scalar indirectLookups;
    Stats::Scalar indirectHits;
    Stats::Scalar indirectMisses;
    Stats::Scalar indirectMispredicted;

  protected:
    const unsigned instShiftAmt;

    ProbePoints::PMUUPtr pmuProbePoint(const char *name);


    ProbePoints::PMUUPtr ppBranches;

    ProbePoints::PMUUPtr ppMisses;

};

#endif // __CPU_PRED_BPRED_UNIT_HH__