33 #ifndef _DEV_ATA_ATAREG_H_
34 #define _DEV_ATA_ATAREG_H_
36 #if defined(__linux__)
40 #include <sys/isa_defs.h>
43 #include <machine/endian.h>
48 #define ATA_BYTE_ORDER LITTLE_ENDIAN
49 #elif defined(BIG_ENDIAN)
50 #define ATA_BYTE_ORDER BIG_ENDIAN
51 #elif defined(_LITTLE_ENDIAN)
52 #define ATA_BYTE_ORDER 1
53 #define LITTLE_ENDIAN 1
54 #elif defined(_BIG_ENDIAN)
55 #define ATA_BYTE_ORDER 0
56 #define LITTLE_ENDIAN 1
58 #error "No endianess defined"
70 #define WDC_CFG_ATAPI_MASK 0xc000
71 #define WDC_CFG_ATAPI 0x8000
72 #define ATA_CFG_REMOVABLE 0x0080
73 #define ATA_CFG_FIXED 0x0040
74 #define ATAPI_CFG_TYPE_MASK 0x1f00
75 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
76 #define ATAPI_CFG_TYPE_DIRECT 0x00
77 #define ATAPI_CFG_TYPE_SEQUENTIAL 0x01
78 #define ATAPI_CFG_TYPE_CDROM 0x05
79 #define ATAPI_CFG_TYPE_OPTICAL 0x07
80 #define ATAPI_CFG_TYPE_NODEVICE 0x1F
81 #define ATAPI_CFG_REMOV 0x0080
82 #define ATAPI_CFG_DRQ_MASK 0x0060
83 #define ATAPI_CFG_STD_DRQ 0x0000
84 #define ATAPI_CFG_IRQ_DRQ 0x0020
85 #define ATAPI_CFG_ACCEL_DRQ 0x0040
86 #define ATAPI_CFG_CMD_MASK 0x0003
87 #define ATAPI_CFG_CMD_12 0x0000
88 #define ATAPI_CFG_CMD_16 0x0001
106 #define WDC_CAP_IORDY 0x0800
107 #define WDC_CAP_IORDY_DSBL 0x0400
108 #define WDC_CAP_LBA 0x0200
109 #define WDC_CAP_DMA 0x0100
110 #define ATA_CAP_STBY 0x2000
111 #define ATAPI_CAP_INTERL_DMA 0x8000
112 #define ATAPI_CAP_CMD_QUEUE 0x4000
113 #define ATAPI_CAP_OVERLP 0x2000
114 #define ATAPI_CAP_ATA_RST 0x1000
116 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
128 #define WDC_EXT_UDMA_MODES 0x0004
129 #define WDC_EXT_MODES 0x0002
130 #define WDC_EXT_GEOM 0x0001
138 #define WDC_MULTI_VALID 0x0100
139 #define WDC_MULTI_MASK 0x00ff
142 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
163 #define WDC_QUEUE_DEPTH_MASK 0x1f
165 #define SATA_SIGNAL_GEN1 0x0002
166 #define SATA_SIGNAL_GEN2 0x0004
167 #define SATA_NATIVE_CMDQ 0x0100
168 #define SATA_HOST_PWR_MGMT 0x0200
171 #define SATA_NONZERO_OFFSETS 0x0002
172 #define SATA_DMA_SETUP_AUTO 0x0004
173 #define SATA_DRIVE_PWR_MGMT 0x0008
176 #define WDC_VER_ATA1 0x0002
177 #define WDC_VER_ATA2 0x0004
178 #define WDC_VER_ATA3 0x0008
179 #define WDC_VER_ATA4 0x0010
180 #define WDC_VER_ATA5 0x0020
181 #define WDC_VER_ATA6 0x0040
182 #define WDC_VER_ATA7 0x0080
183 #define WDC_VER_ATA8 0x0100
184 #define WDC_VER_ATA9 0x0200
185 #define WDC_VER_ATA10 0x0400
186 #define WDC_VER_ATA11 0x0800
187 #define WDC_VER_ATA12 0x1000
188 #define WDC_VER_ATA13 0x2000
189 #define WDC_VER_ATA14 0x4000
192 #define WDC_CMD1_NOP 0x4000
193 #define WDC_CMD1_RB 0x2000
194 #define WDC_CMD1_WB 0x1000
195 #define WDC_CMD1_HPA 0x0400
196 #define WDC_CMD1_DVRST 0x0200
197 #define WDC_CMD1_SRV 0x0100
198 #define WDC_CMD1_RLSE 0x0080
199 #define WDC_CMD1_AHEAD 0x0040
200 #define WDC_CMD1_CACHE 0x0020
201 #define WDC_CMD1_PKT 0x0010
202 #define WDC_CMD1_PM 0x0008
203 #define WDC_CMD1_REMOV 0x0004
204 #define WDC_CMD1_SEC 0x0002
205 #define WDC_CMD1_SMART 0x0001
207 #define ATAPI_CMD2_FCE 0x2000
208 #define ATAPI_CMD2_FC 0x1000
209 #define ATAPI_CMD2_DCO 0x0800
210 #define ATAPI_CMD2_48AD 0x0400
211 #define ATAPI_CMD2_AAM 0x0200
212 #define ATAPI_CMD2_SM 0x0100
213 #define ATAPI_CMD2_SF 0x0040
214 #define ATAPI_CMD2_PUIS 0x0020
215 #define WDC_CMD2_RMSN 0x0010
216 #define ATA_CMD2_APM 0x0008
217 #define ATA_CMD2_CFA 0x0004
218 #define ATA_CMD2_RWQ 0x0002
219 #define WDC_CMD2_DM 0x0001
221 #define ATAPI_CMDE_MSER 0x0004
222 #define ATAPI_CMDE_TEST 0x0002
223 #define ATAPI_CMDE_SLOG 0x0001
230 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
243 #define ATA_HWRES_CBLID 0x2000
244 #define ATA_HWRES_D1_PDIAG 0x0800
245 #define ATA_HWRES_D1_CSEL 0x0400
246 #define ATA_HWRES_D1_JUMP 0x0200
247 #define ATA_HWRES_D0_SEL 0x0040
248 #define ATA_HWRES_D0_DASP 0x0020
249 #define ATA_HWRES_D0_PDIAG 0x0010
250 #define ATA_HWRES_D0_DIAG 0x0008
251 #define ATA_HWRES_D0_CSEL 0x0004
252 #define ATA_HWRES_D0_JUMP 0x0002
253 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
264 #define WDC_RMSN_SUPP_MASK 0x0003
265 #define WDC_RMSN_SUPP 0x0001
267 #define WDC_SEC_LEV_MAX 0x0100
268 #define WDC_SEC_ESE_SUPP 0x0020
269 #define WDC_SEC_EXP 0x0010
270 #define WDC_SEC_FROZEN 0x0008
271 #define WDC_SEC_LOCKED 0x0004
272 #define WDC_SEC_EN 0x0002
273 #define WDC_SEC_SUPP 0x0001
276 #define ATAPI_CFA_MAX_MASK 0x0FFF
277 #define ATAPI_CFA_MODE1_DIS 0x1000
278 #define ATAPI_CFA_MODE1_REQ 0x2000
279 #define ATAPI_CFA_WORD160 0x8000
283 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
292 #undef ATA_BYTE_ORDER
uint8_t atap_piomode_supp
uint16_t atap_curcylinders
uint8_t atap_capabilities1
uint16_t atap_sata_features_en
uint8_t atap_media_serial[60]
uint16_t atap_sata_features_supp
uint8_t atap_acoustic_val
uint16_t atap_hwreset_res
uint8_t atap_olddmatiming
uint8_t atap_curmulti_valid
uint8_t atap_udmamode_supp
uint16_t atap_dmatiming_recom
uint8_t atap_acoustic_def
uint16_t __reserved10[49]
uint8_t atap_udmamode_act
uint16_t atap_curcapacity[2]
uint16_t atap_capabilities2
uint16_t atap_dmatiming_mimi
uint16_t atap_mpasswd_rev
uint8_t atap_dmamode_supp
uint16_t atap_piotiming_iordy
uint16_t atap_sata_reserved
uint8_t atap_oldpiotiming