Recent Happenings

• Summer 2018: Will be interning at Google Madison.
• May 2018: About to give PhD preliminary exam.
• April 2018: Awarded the Landweber NCR Graduate Fellowship in Distributed Systems.
• March 2018: Presented DVM at ASPLOS 2018, Williamsburg, VA.
• March 2018: Presented HOPS+ at NVMW 2018, San Diego, CA.
• February 2018: Got married to Sukriti Singh!
• January 2018: ASPLOS'17 paper on WHISPER gets Honorable Mention in IEEE Micro Top Picks 2018.
• November 2017: Devirtualized Memory (DVM) paper accepted for ASPLOS '18 .

Publications

• Devirtualizing virtual memory for heterogeneous systems
  Swapnil Haria, Mark D. Hill, Michael M. Swift
  23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2018).
  Paper Presentation
• Efficient Durability for Lock-based Code
  Swapnil Haria, Pratyush Mahapatra, Mark D. Hill, Michael M. Swift
  9th Annual Non-Volatile Memories Workshop (NVMW 2018)
  Paper Presentation
• An Analysis of Persistent Memory Use with WHISPER
  Sanketh Nalli, Swapnil Haria, Mark D. Hill, Michael M. Swift, Haris Volos, Kimberly Keeton
  22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017).
  IEEE Micro Top Picks 2018 Honorable Mentions
  Paper Presentation
• Hands-Off Persistence System (HOPS)
  Swapnil Haria, Sanketh Nalli, Mark D. Hill, Michael M. Swift, Haris Volos, Kimberly Keeton
  8th Annual Non-Volatile Memories Workshop (NVMW 2017)
  Paper Presentation
• Optimal Mapping of Multiple Packet Lookup Schemes onto FPGA
  Swapnil Haria, Viktor Prasanna.
  2013 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2013), Mexico, Dec 2013.
  Paper Presentation
• Architecture and Performance Models for Scalable IP Lookup Engines on FPGA
  Yi-Hua E. Yang, Yun Qu, Swapnil Haria, Viktor Prasanna.
  14th International Conference on High Performance Switching and Routing (IEEE HPSR '13), Taipei, July 2013.
  Paper Presentation
• Power-Efficient and Scalable Virtual Router Architecture on FPGA
  Swapnil Haria, Thilan Ganegedara, Viktor Prasanna.
  2012 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), Mexico, Dec 2012.
  Paper Presentation
• AutoMapper -An automated tool for optimal hardware resource allocation for networking applications on FPGA (Poster)
  Swapnil Haria, Viktor Prasanna.
  21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2012), California, Feb 2013.
  Abstract Poster

Courses

• CS 799: Master's Research (Independent Study under Professor Mark Hill, looking at optimizing the cache hierarchy for non-volatile memory)
• CS 760: Machine Learning
• MHR 723: Business Strategy

• CS 799: Master's Research (Independent Study under Professor Mark Hill, looking at optimizing the cache hierarchy for non-volatile memory)
• CS 540: Introduction to Artificial Intelligence
• CS 577: Introduction to Algorithms

• CS 799: Master's Research (Independent Study under Professor Mark Hill, in the area of efficient address translation for managed languages)
• CS 757: Advanced Computer Architecture II
  Research Project Resources: Project Report, Presentation
• CS 736: Advanced Operating Systems
  Research Project Resources: Project Report, Presentation

• CS 799: Master's Research (Independent Study under Professor Mark Hill, in the area of Virtual Memory)
  Resources: Final Report
• CS 752: Advanced Computer Architecture I
  Research Project Resources: Project Report, Presentation
• CS 537: Introduction to Operating Systems

• Kernel Developer, Oracle, Santa Clara from May 2015 to August 2015.
  Worked with the NUMA/Scheduling team in the Solaris Core Kernel Group.
• ASIC Engineer, NVIDIA, Bangalore, India from January 2013 to July 2014.
  Involved in the functional verification of the Denver CPU.
• Research Fellow, Viterbi School of Engineering, University of Southern California from May to July 2012.
  Worked on various problems (Summary Poster) in the context of IP lookup on FPGA, under Professor Viktor Prasanna.
• Research Intern, Indira Gandhi Centre for Atomic Research, India from May to July 2011.
  Contributed to a real-time monitoring system for a Fast Breeder Reactor.