#include <timing.hh>

Inheritance diagram for TimingSimpleCPU:

Classes
class	DcachePort

class	FetchTranslation

class	IcachePort

struct	IprEvent

class	SplitFragmentSenderState

class	SplitMainSenderState

class	TimingCPUPort
	A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle. More...

Public Member Functions
	TimingSimpleCPU (TimingSimpleCPUParams *params)

virtual	~TimingSimpleCPU ()

void	init () override

DrainState	drain () override

void	drainResume () override

void	switchOut () override

void	takeOverFrom (BaseCPU *oldCPU) override

void	verifyMemoryMode () const override

void	activateContext (ThreadID thread_num) override

void	suspendContext (ThreadID thread_num) override

Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags) override

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res) override

void	fetch ()

void	sendFetch (const Fault &fault, RequestPtr req, ThreadContext *tc)

void	completeIfetch (PacketPtr)

void	completeDataAccess (PacketPtr pkt)

void	advanceInst (const Fault &fault)

bool	isSquashed () const
	This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed. More...

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging). More...

void	finishTranslation (WholeTranslationState *state)
	Finish a DTB translation. More...

Public Member Functions inherited from BaseSimpleCPU
	BaseSimpleCPU (BaseSimpleCPUParams *params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	init () override

Addr	dbg_vtophys (Addr addr)

void	checkForInterrupts ()

void	setupFetchRequest (Request *req)

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override

void	regStats () override

void	resetStats () override

void	startup () override

void	countInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override

Protected Member Functions
MasterPort &	getDataPort () override
	Return a reference to the data port. More...

MasterPort &	getInstPort () override
	Return a reference to the instruction port. More...

Protected Member Functions inherited from BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

Private Types
typedef EventWrapper < TimingSimpleCPU,&TimingSimpleCPU::fetch >	FetchEvent

Private Member Functions
void	threadSnoop (PacketPtr pkt, ThreadID sender)

void	sendData (RequestPtr req, uint8_t data, uint64_t res, bool read)

void	sendSplitData (RequestPtr req1, RequestPtr req2, RequestPtr req, uint8_t *data, bool read)

void	translationFault (const Fault &fault)

PacketPtr	buildPacket (RequestPtr req, bool read)

void	buildSplitPacket (PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr req1, RequestPtr req2, RequestPtr req, uint8_t *data, bool read)

bool	handleReadPacket (PacketPtr pkt)

bool	handleWritePacket ()

void	updateCycleCounts ()

bool	isDrained ()
	Check if a system is in a drained state. More...

bool	tryCompleteDrain ()
	Try to complete a drain request. More...

Private Attributes
FetchTranslation	fetchTranslation

IcachePort	icachePort

DcachePort	dcachePort

PacketPtr	ifetch_pkt

PacketPtr	dcache_pkt

Cycles	previousCycle

FetchEvent	fetchEvent

Additional Inherited Members
Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

Public Attributes inherited from BaseSimpleCPU
Trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

TheISA::MachInst	inst
	Current instruction. More...

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Protected Types inherited from BaseSimpleCPU
enum	Status { Idle, Running, Faulting, ITBWaitResponse, IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse, DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch }

Protected Attributes inherited from BaseSimpleCPU
ThreadID	curThread

BPredUnit *	branchPred

Status	_status

Detailed Description

Definition at line 51 of file timing.hh.

Member Typedef Documentation

typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> TimingSimpleCPU::FetchEvent

private

Definition at line 318 of file timing.hh.

Constructor & Destructor Documentation

TimingSimpleCPU::TimingSimpleCPU ( TimingSimpleCPUParams * params )

Definition at line 80 of file timing.cc.

References BaseSimpleCPU::_status, and BaseSimpleCPU::Idle.

TimingSimpleCPU::~TimingSimpleCPU ( )

virtual

Definition at line 90 of file timing.cc.

Member Function Documentation

void TimingSimpleCPU::activateContext ( ThreadID thread_num )

override

Definition at line 203 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseSimpleCPU::Running, Event::scheduled(), and BaseSimpleCPU::threadInfo.

void TimingSimpleCPU::advanceInst ( const Fault & fault )

Definition at line 665 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::advancePC(), BaseSimpleCPU::curThread, DPRINTF, BaseSimpleCPU::Faulting, fetch(), fetchEvent, NoFault, BaseSimpleCPU::Running, SimpleExecContext::stayAtPC, BaseSimpleCPU::threadInfo, and tryCompleteDrain().

Referenced by completeDataAccess(), completeIfetch(), sendFetch(), and translationFault().

PacketPtr TimingSimpleCPU::buildPacket	(	RequestPtr	req,
		bool	read
	)

private

Definition at line 373 of file timing.cc.

References Packet::createRead(), and Packet::createWrite().

Referenced by buildSplitPacket(), and sendData().

void TimingSimpleCPU::buildSplitPacket	(	PacketPtr &	pkt1,
		PacketPtr &	pkt2,
		RequestPtr	req1,
		RequestPtr	req2,
		RequestPtr	req,
		uint8_t *	data,
		bool	read
	)

private

Definition at line 379 of file timing.cc.

References buildPacket(), Packet::cmd, data, Packet::dataDynamic(), Packet::dataStatic(), Request::getFlags(), Request::getSize(), Request::isMmappedIpr(), Flags< T >::isSet(), Request::NO_ACCESS, MemCmd::responseCommand(), and Packet::senderState.

Referenced by sendSplitData().

void TimingSimpleCPU::completeDataAccess ( PacketPtr pkt )

void TimingSimpleCPU::completeIfetch ( PacketPtr pkt )

DrainState TimingSimpleCPU::drain ( )

override

Definition at line 95 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, DPRINTF, Drained, Draining, fetchEvent, BaseSimpleCPU::Idle, isDrained(), BaseSimpleCPU::Running, and Event::scheduled().

void TimingSimpleCPU::drainResume ( )

override

Definition at line 119 of file timing.cc.

References BaseSimpleCPU::_status, ThreadContext::Active, BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseSimpleCPU::Running, Event::scheduled(), ArmISA::system, BaseSimpleCPU::threadInfo, and verifyMemoryMode().

void TimingSimpleCPU::fetch ( )

void TimingSimpleCPU::finishTranslation ( WholeTranslationState * state )

Finish a DTB translation.

Parameters

state The DTB translation state.

Definition at line 565 of file timing.cc.

References BaseSimpleCPU::_status, WholeTranslationState::data, WholeTranslationState::deleteReqs(), WholeTranslationState::getFault(), WholeTranslationState::isPrefetch(), WholeTranslationState::isSplit, WholeTranslationState::mainReq, WholeTranslationState::mode, NoFault, BaseTLB::Read, WholeTranslationState::res, BaseSimpleCPU::Running, sendData(), sendSplitData(), WholeTranslationState::setNoFault(), WholeTranslationState::sreqHigh, WholeTranslationState::sreqLow, and translationFault().

MasterPort& TimingSimpleCPU::getDataPort ( )

inlineoverrideprotected

Return a reference to the data port.

Definition at line 263 of file timing.hh.

References dcachePort.

MasterPort& TimingSimpleCPU::getInstPort ( )

inlineoverrideprotected

Return a reference to the instruction port.

Definition at line 266 of file timing.hh.

References icachePort.

bool TimingSimpleCPU::handleReadPacket ( PacketPtr pkt )

private

bool TimingSimpleCPU::handleWritePacket ( )

private

Definition at line 470 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::curThread, dcache_pkt, dcachePort, BaseSimpleCPU::DcacheRetry, BaseSimpleCPU::DcacheWaitResponse, SimpleThread::getTC(), GenericISA::handleIprWrite(), Request::isMmappedIpr(), Packet::req, MasterPort::sendTimingReq(), SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

void TimingSimpleCPU::init ( )

override

Definition at line 68 of file timing.cc.

References BaseSimpleCPU::init().

Fault TimingSimpleCPU::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags
	)

overridevirtual

bool TimingSimpleCPU::isDrained ( )

inlineprivate

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
Stay at PC is true.
A fetch event is scheduled. Normally this would never be the case with microPC() == 0, but right after a context is activated it can happen.

Definition at line 345 of file timing.hh.

References BaseSimpleCPU::curThread, fetchEvent, SimpleThread::microPC(), Event::scheduled(), SimpleExecContext::stayAtPC, SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by drain(), and tryCompleteDrain().

bool TimingSimpleCPU::isSquashed ( ) const

inline

This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

This always returns false for the simple timing CPU as it never executes any instructions speculatively. @ return Is the current instruction squashed?

Definition at line 302 of file timing.hh.

void TimingSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 999 of file timing.cc.

References dcachePort, and MasterPort::printAddr().