CS/ECE 552 Spring 2022

Aligned Single-Cycle Memory Specification

Before building your cache, you should use this memory to update and test your processor's interface to properly handle unaligned accesses. Many processors (e.g., MIPS) are byte addressable, but require that all accesses be aligned to their natural size (i.e., byte loads and stores can access any individual byte, but word loads and stores must access aligned words). Since your processor only has word loads and stores, this is pretty simple (to support byte stores, the memory would need byte write enable signals; to support byte loads, either the memory or the processor needs a mux to select the right byte). Notice that the memory always returns aligned data even on a misaligned load. Moreover, note that the memory will not write anything when a store is unaligned.

The verilog source (memory2c_align.v) and synthesizable version (memory2c_align.syn.v) were included in the project tar.

Since your single-cycle design must fetch instructions as well as read or write data in the same cycle, you will want to use two instances of this memory -- one for data, and one for instructions.

                              +-------------+
        data_in[15:0] >-------|             |--------> data_out[15:0]
           addr[15:0] >-------| 65536 word  |
               enable >-------| by 16 bit   |--------> err
                   wr >-------| memory      |
                  clk >-------|             |
                  rst >-------|             |
           createdump >-------|             |
                              +-------------+
      

During each cycle, the "enable" and "wr" inputs determine what function the memory will perform. On a unaligned access err is set.

Expected Behavior

When testing your aligned memory implementation, the expected behavior of your processor is that you should propagate your error signal from whatever stage it occurs until the end of your pipeline (e.g., if the unaligned access occurs in Fetch, pass it to WB, and raise the err signal at the end). This is done to allow any instructions farther along in the pipeline to complete before the err signal is asserted. You should see that your test still passes, and that the err signal is raised. If you look further into what happens under the hood, you should see that only the instructions before the unaligned one complete successfully.

How to Run

To run tests, you will also need to use the -align flag in wsrun.pl -- this flag ensures that the golden version knows to run in word aligned mode. Otherwise, you can continue running the same way you ran in Phase 2 (e.g., wsrun.pl -align -pipe -prog <...> proc_hier_pbench *.v).