CS/ECE 552 Spring 2022
Course Homepage
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The CS/ECE 552 term project is the complete functional design of a microprocessor called the WISC-SP22. All components of your design will be written in Verilog. As with the course homeworks, the CS/ECE 552 Verilog restrictions apply, and all final code is expected to pass the Vcheck program.
The project will be completed individually.
The specifics of the microarchitecture and WISC-SP22 architecture will be posted above under "Important Documents."
The project will progress in several distinct stages. Some of these stages are enforced through grading deadlines; others are not. The key deadlines are listed above.
Unless approved by the instructor in advance, you may turn in each phase of the project up to 48 hours late, with a 10% penalty per day, up to two days max. Any submissions over two days late will receive a zero. I strongly recommend that you do not avail yourself of this option; your hard work deserves full credit. Additionally, you may use up to three "free" late days for the project. If you need these free late days, I strongly advise you to utilize them for the coding phases (Phases 1-3).