CS/ECE 552 Spring 2022

Enforced rule for all Verilog submissions:

• Every verilog file must define EXACTLY one module. If you define multiple modules in a verilog file, it will be considered a violation of cs552 verilog rules.
• If a verilog file is called xor15.v, the module it contains must be named xor15.v
  • The filename and module name must have an EXACT one-to-one match
  • YOU CANNOT have a file called 15xor.v and in it create a module called adder.v
• Run the name-convention-check script
• Any instantiation of a module must include port names along with net-names, i.e.:

        clkrst c0(clk, rst) is NOT OK
        clkrst c0(.clk(clk), .rst(rst)) is CORRECT
      

Recommended Hierarchy and Filenaming conventions (For HW2-HW5 and project demos):

• Your top-level module must be called foo_hier.v
• It MUST contain clkrst.v
• Its interface (input/output ports) should be identical to what is suggested in your homework problems
• Name the module you are designing foo and instantiate foo inside foo_hier.v
• For example, see rf_hier.v and rf.v here for the register file.
• You will follow a similar convention for your project.
• Create cpu.v and cpu_hier.v
• Name all testbenches with the _bench suffix

For project:

We will follow this same convention for your project.

• Your top most level with just the processor MUST be called proc.v. A template for will be provided for this.
• You must use the to-be-provided proc_hier.v which will instantiate the clock generator and your processor.
• You must use the to-be-provided proc_hier_bench.v testbench. If you cannot absolutely use this, email the instructor and TA to find a solution.