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Verilog Filename Convention Checking

As with several other pages, for this tutorial we assume you have added /u/s/i/sinclair/public/html/courses/cs552/spring2022/handouts/bins/ to your PATH. In this directory, you will find a script called name-covention-check.

Running the name-covention-check from a directory and it will check all Verilog files in that directory. For example: 

          prompt> name-convention-check

          Checking file 16AND.v: ERROR: (name mismatch) Found module AND16 (expected 16AN
          D) in 16AND.v, at line 1:module AND16(InA, InB, Out);

          Checking file 16OR.v: ERROR: (name mismatch) Found module OR16 (expected 16OR)
          in 16OR.v, at line 1:module OR16(InA, InB, Out);

          Checking file 16XOR.v: ERROR: (name mismatch) Found module XOR16 (expected 16XO
          R) in 16XOR.v, at line 1:module XOR16(InA, InB, Out);

          Checking file ALU_hier.v: OK: Found module ALU_hier (expected ALU_hier) in ALU_
          hier.v, at line 1:module ALU_hier(A, B, Cin, Op, invA, invB, sign, Out, OFL, Ze
          ro);

          Checking file ALU.v: OK: Found module ALU (expected ALU) in ALU.v, at line 1:mo
          dule ALU(A, B, Cin, Op, invA, invB, sign, Out, OFL, Zero);

          Checking file CLA1.v: OK: Found module CLA1 (expected CLA1) in CLA1.v, at line
          1:module CLA1(A, B, Cin, G, P, Out);

          Checking file CLA4.v: OK: Found module CLA4 (expected CLA4) in CLA4.v, at line
          1:module CLA4(A, B, Cin, G, P, Out);
          .....

          Examined 12 files, Found 3 errors