Your shell is probably not in bash (type bash (enter), then try again)
You did not added the required lines to your .bashrc. See ModelSim Tutorial page.
2. sh: dc_shell-t : command not found
3. Cannot execute dc_shell-t. Something is wrong. Did you perform all the environment setup steps?
Probably an environment problem. Did you follow the environment setup instructions on the Synthesis page?
Add the specified line to .bashrc, logout and log back in
4. ERROR ./(filename).v is redefined
You probably added a file twice in your list. Delete one of them. Run with -check again.
This error you MUST fix.
5. Warning: Unable to resolve reference 'foo' in 'bar'
6. Warning: Design 'xxx' has '4' unresolved references.
These warnings you MUST fix. This means you forgot to add the file foo.v to your file list.
If you ignore this warning and continue with --cmd=synth, synthesis will *appear* to succeed. But if you look at the cell report you will see cell area zero against some cells. For example:
mux2_1 0.000000 1 0.000000 b
mux2_1_16bit_0 0.000000 1 0.000000 b, h
mux2_1_16bit_1 0.000000 1 0.000000 b, h
mux2_1_16bit_2 0.000000 1 0.000000 b, h
mux4_1_16bit 0.000000 1 0.000000 b, h
This is incomplete synthesis.
7. Error: Cannot find the specified driving cell in memory. (UID-993)
8. Error: Could not read the following target libraries:
You probably did not add the line "source /s/synopsys/@sys/synopsys_env.sh" to .bashrc or run this script, as mentioned in the Synthesis page.
You probably did not copy the .synopsys_dc.setup file
Notice the name has a dot as the first character.
You probably did not logout and log back in after making these changes.
10. Can't find my error here
Email the the Instructor and TAs. Include the full text of the error and include your Verilog file on which the warning or error was reported as an attachment in that email.