Links to specific parts of document:
You probably added a file twice in your list. Delete one of them. Run with -check again. This error you MUST fix.
These warnings you MUST fix. This means you forgot to add the file foo.v to your file list.
If you ignore this warning and continue with --cmd=synth, synthesis will *appear* to succeed. But if you look at the cell report you will see cell area zero against some cells. For example:
mux2_1 0.000000 1 0.000000 b
mux2_1_16bit_0 0.000000 1 0.000000 b, h
mux2_1_16bit_1 0.000000 1 0.000000 b, h
mux2_1_16bit_2 0.000000 1 0.000000 b, h
mux4_1_16bit 0.000000 1 0.000000 b, h
This is incomplete synthesis.
"source /s/synopsys/@sys/synopsys_env.sh" to .bashrc or run this script, as mentioned in the Synthesis page.
Email the the Instructor and TAs. Include the full text of the error and include your Verilog file on which the warning or error was reported as an attachment in that email.