_status | BaseSimpleCPU | protected |
activateContext(ThreadID thread_num) override | AtomicSimpleCPU | |
activeThreads | BaseSimpleCPU | |
advancePC(const Fault &fault) | BaseSimpleCPU | |
AtomicSimpleCPU(AtomicSimpleCPUParams *params) | AtomicSimpleCPU | |
BaseSimpleCPU(BaseSimpleCPUParams *params) | BaseSimpleCPU | |
branchPred | BaseSimpleCPU | protected |
checker | BaseSimpleCPU | |
checkForInterrupts() | BaseSimpleCPU | |
checkPcEventQueue() | BaseSimpleCPU | protected |
countInst() | BaseSimpleCPU | |
curMacroStaticInst | BaseSimpleCPU | |
curStaticInst | BaseSimpleCPU | |
curThread | BaseSimpleCPU | protected |
data_read_req | AtomicSimpleCPU | private |
data_write_req | AtomicSimpleCPU | private |
dbg_vtophys(Addr addr) | BaseSimpleCPU | |
dcache_access | AtomicSimpleCPU | private |
dcache_latency | AtomicSimpleCPU | private |
dcachePort | AtomicSimpleCPU | private |
DcacheRetry enum value | BaseSimpleCPU | protected |
DcacheWaitResponse enum value | BaseSimpleCPU | protected |
DcacheWaitSwitch enum value | BaseSimpleCPU | protected |
drain() override | AtomicSimpleCPU | |
drainResume() override | AtomicSimpleCPU | |
DTBWaitResponse enum value | BaseSimpleCPU | protected |
fastmem | AtomicSimpleCPU | private |
Faulting enum value | BaseSimpleCPU | protected |
getDataPort() override | AtomicSimpleCPU | inlineprotected |
getInstPort() override | AtomicSimpleCPU | inlineprotected |
haltContext(ThreadID thread_num) override | BaseSimpleCPU | |
icachePort | AtomicSimpleCPU | private |
IcacheRetry enum value | BaseSimpleCPU | protected |
IcacheWaitResponse enum value | BaseSimpleCPU | protected |
IcacheWaitSwitch enum value | BaseSimpleCPU | protected |
Idle enum value | BaseSimpleCPU | protected |
ifetch_req | AtomicSimpleCPU | private |
init() override | AtomicSimpleCPU | |
initiateMemRead(Addr addr, unsigned size, Request::Flags flags) override | AtomicSimpleCPU | virtual |
inst | BaseSimpleCPU | |
isDrained() | AtomicSimpleCPU | inlineprivate |
ITBWaitResponse enum value | BaseSimpleCPU | protected |
locked | AtomicSimpleCPU | private |
numSimulatedInsts() | BaseCPU | inlinestatic |
numSimulatedOps() | BaseCPU | inlinestatic |
postExecute() | BaseSimpleCPU | |
ppCommit | AtomicSimpleCPU | private |
preExecute() | BaseSimpleCPU | |
printAddr(Addr a) | AtomicSimpleCPU | |
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags) override | AtomicSimpleCPU | virtual |
regProbePoints() override | AtomicSimpleCPU | |
regStats() override | BaseSimpleCPU | |
resetStats() override | BaseSimpleCPU | |
Running enum value | BaseSimpleCPU | protected |
serializeThread(CheckpointOut &cp, ThreadID tid) const override | BaseSimpleCPU | |
setupFetchRequest(Request *req) | BaseSimpleCPU | |
simulate_data_stalls | AtomicSimpleCPU | private |
simulate_inst_stalls | AtomicSimpleCPU | private |
startup() override | BaseSimpleCPU | |
Status enum name | BaseSimpleCPU | protected |
suspendContext(ThreadID thread_num) override | AtomicSimpleCPU | |
swapActiveThread() | BaseSimpleCPU | protected |
switchOut() override | AtomicSimpleCPU | |
takeOverFrom(BaseCPU *oldCPU) override | AtomicSimpleCPU | |
threadInfo | BaseSimpleCPU | |
threadSnoop(PacketPtr pkt, ThreadID sender) | AtomicSimpleCPU | protected |
tick() | AtomicSimpleCPU | private |
tickEvent | AtomicSimpleCPU | private |
totalInsts() const override | BaseSimpleCPU | |
totalOps() const override | BaseSimpleCPU | |
traceData | BaseSimpleCPU | |
tryCompleteDrain() | AtomicSimpleCPU | private |
unserializeThread(CheckpointIn &cp, ThreadID tid) override | BaseSimpleCPU | |
verifyMemoryMode() const override | AtomicSimpleCPU | |
wakeup(ThreadID tid) override | BaseSimpleCPU | |
width | AtomicSimpleCPU | private |
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) override | AtomicSimpleCPU | virtual |
~AtomicSimpleCPU() | AtomicSimpleCPU | virtual |
~BaseSimpleCPU() | BaseSimpleCPU | virtual |