| _destMiscRegIdx | BaseO3DynInst< Impl > | protected |
| _destMiscRegVal | BaseO3DynInst< Impl > | protected |
| _destRegIdx | BaseDynInst< Impl > | protected |
| _flatDestRegIdx | BaseDynInst< Impl > | protected |
| _numDestMiscRegs | BaseO3DynInst< Impl > | protected |
| _prevDestRegIdx | BaseDynInst< Impl > | protected |
| _readySrcRegIdx | BaseDynInst< Impl > | protected |
| _srcRegIdx | BaseDynInst< Impl > | protected |
| armMonitor(Addr address) | BaseDynInst< Impl > | inlinevirtual |
| asid | BaseDynInst< Impl > | |
| AtCommit enum value | BaseDynInst< Impl > | protected |
| BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu) | BaseDynInst< Impl > | |
| BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop) | BaseDynInst< Impl > | |
| BaseDynInstPtr typedef | BaseDynInst< Impl > | |
| BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu) | BaseO3DynInst< Impl > | |
| BaseO3DynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop) | BaseO3DynInst< Impl > | |
| BlockingInst enum value | BaseDynInst< Impl > | protected |
| branchTarget() const | BaseDynInst< Impl > | inline |
| calcEA() | BaseO3DynInst< Impl > | inline |
| CanCommit enum value | BaseDynInst< Impl > | protected |
| CanIssue enum value | BaseDynInst< Impl > | protected |
| CCReg typedef | BaseO3DynInst< Impl > | |
| clearCanCommit() | BaseDynInst< Impl > | inline |
| clearCanIssue() | BaseDynInst< Impl > | inline |
| clearInIQ() | BaseDynInst< Impl > | inline |
| clearInROB() | BaseDynInst< Impl > | inline |
| clearIssued() | BaseDynInst< Impl > | inline |
| clearSerializeAfter() | BaseDynInst< Impl > | inline |
| clearSerializeBefore() | BaseDynInst< Impl > | inline |
| Committed enum value | BaseDynInst< Impl > | protected |
| completeAcc(PacketPtr pkt) | BaseO3DynInst< Impl > | |
| Completed enum value | BaseDynInst< Impl > | protected |
| contextId() const | BaseDynInst< Impl > | inline |
| cpu | BaseDynInst< Impl > | |
| cpuId() const | BaseDynInst< Impl > | inline |
| decref() | RefCounted | inline |
| demapDataPage(Addr vaddr, uint64_t asn) | BaseDynInst< Impl > | inline |
| demapInstPage(Addr vaddr, uint64_t asn) | BaseDynInst< Impl > | inline |
| demapPage(Addr vaddr, uint64_t asn) | BaseDynInst< Impl > | inlinevirtual |
| destRegIdx(int i) const | BaseDynInst< Impl > | inline |
| doneEACalc() | BaseDynInst< Impl > | inline |
| doneTargCalc() | BaseDynInst< Impl > | inline |
| dump() | BaseDynInst< Impl > | |
| dump(std::string &outstring) | BaseDynInst< Impl > | |
| DynInstPtr typedef | BaseDynInst< Impl > | |
| EACalcDone enum value | BaseDynInst< Impl > | protected |
| eaSrcsReady() | BaseDynInst< Impl > | |
| effAddr | BaseDynInst< Impl > | |
| EffAddrValid enum value | BaseDynInst< Impl > | protected |
| effAddrValid() const | BaseDynInst< Impl > | inline |
| effSize | BaseDynInst< Impl > | |
| execute() | BaseO3DynInst< Impl > | |
| Executed enum value | BaseDynInst< Impl > | protected |
| ExtMachInst typedef | BaseO3DynInst< Impl > | |
| fault | BaseDynInst< Impl > | |
| finishTranslation(WholeTranslationState *state) | BaseDynInst< Impl > | inline |
| Flags enum name | BaseDynInst< Impl > | protected |
| flattenDestReg(int idx, TheISA::RegIndex flattened_dest) | BaseDynInst< Impl > | inline |
| flattenedDestRegIdx(int idx) const | BaseDynInst< Impl > | inline |
| FloatReg typedef | BaseO3DynInst< Impl > | |
| FloatRegBits typedef | BaseO3DynInst< Impl > | |
| forwardOldRegs() | BaseO3DynInst< Impl > | inline |
| getAddrMonitor() | BaseDynInst< Impl > | inlinevirtual |
| getCpuPtr() | BaseDynInst< Impl > | inline |
| getEA() const | BaseDynInst< Impl > | inlinevirtual |
| getFault() const | BaseDynInst< Impl > | inline |
| getInstListIt() | BaseDynInst< Impl > | inline |
| hasRequest() | BaseDynInst< Impl > | inline |
| hitExternalSnoop() const | BaseDynInst< Impl > | inline |
| hitExternalSnoop(bool f) | BaseDynInst< Impl > | inline |
| HitExternalSnoop enum value | BaseDynInst< Impl > | protected |
| hwrei() | BaseO3DynInst< Impl > | virtual |
| ImplCPU typedef | BaseDynInst< Impl > | |
| ImplState typedef | BaseDynInst< Impl > | |
| incref() | RefCounted | inline |
| initiateAcc() | BaseO3DynInst< Impl > | |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags) | BaseDynInst< Impl > | |
| ExecContext::initiateMemRead(Addr addr, unsigned int size, Request::Flags flags) | ExecContext | inlinevirtual |
| initiateTranslation(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint64_t *res, BaseTLB::Mode mode) | BaseDynInst< Impl > | inline |
| initVars() | BaseO3DynInst< Impl > | private |
| instAddr() const | BaseDynInst< Impl > | inline |
| instFlags | BaseDynInst< Impl > | protected |
| instListIt | BaseDynInst< Impl > | |
| instResult | BaseDynInst< Impl > | protected |
| IntReg typedef | BaseO3DynInst< Impl > | |
| IqEntry enum value | BaseDynInst< Impl > | protected |
| isAtCommit() | BaseDynInst< Impl > | inline |
| isCall() const | BaseDynInst< Impl > | inline |
| isCommitted() const | BaseDynInst< Impl > | inline |
| isCompleted() const | BaseDynInst< Impl > | inline |
| isCondCtrl() const | BaseDynInst< Impl > | inline |
| isCondDelaySlot() const | BaseDynInst< Impl > | inline |
| isControl() const | BaseDynInst< Impl > | inline |
| isDataPrefetch() const | BaseDynInst< Impl > | inline |
| isDelayedCommit() const | BaseDynInst< Impl > | inline |
| isDirectCtrl() const | BaseDynInst< Impl > | inline |
| isExecuted() const | BaseDynInst< Impl > | inline |
| isFirstMicroop() const | BaseDynInst< Impl > | inline |
| isFloating() const | BaseDynInst< Impl > | inline |
| isIndirectCtrl() const | BaseDynInst< Impl > | inline |
| isInIQ() const | BaseDynInst< Impl > | inline |
| isInLSQ() const | BaseDynInst< Impl > | inline |
| isInROB() const | BaseDynInst< Impl > | inline |
| isInstPrefetch() const | BaseDynInst< Impl > | inline |
| isInteger() const | BaseDynInst< Impl > | inline |
| isIprAccess() const | BaseDynInst< Impl > | inline |
| isIssued() const | BaseDynInst< Impl > | inline |
| isLastMicroop() const | BaseDynInst< Impl > | inline |
| isLoad() const | BaseDynInst< Impl > | inline |
| isMacroop() const | BaseDynInst< Impl > | inline |
| isMemBarrier() const | BaseDynInst< Impl > | inline |
| isMemRef() const | BaseDynInst< Impl > | inline |
| isMicroBranch() const | BaseDynInst< Impl > | inline |
| isMicroop() const | BaseDynInst< Impl > | inline |
| isNonSpeculative() const | BaseDynInst< Impl > | inline |
| isNop() const | BaseDynInst< Impl > | inline |
| isQuiesce() const | BaseDynInst< Impl > | inline |
| isReadySrcRegIdx(int idx) const | BaseDynInst< Impl > | inline |
| isResultReady() const | BaseDynInst< Impl > | inline |
| isReturn() const | BaseDynInst< Impl > | inline |
| isSerializeAfter() const | BaseDynInst< Impl > | inline |
| isSerializeBefore() const | BaseDynInst< Impl > | inline |
| isSerializeHandled() | BaseDynInst< Impl > | inline |
| isSerializing() const | BaseDynInst< Impl > | inline |
| isSquashAfter() const | BaseDynInst< Impl > | inline |
| isSquashed() const | BaseDynInst< Impl > | inline |
| isSquashedInIQ() const | BaseDynInst< Impl > | inline |
| isSquashedInLSQ() const | BaseDynInst< Impl > | inline |
| isSquashedInROB() const | BaseDynInst< Impl > | inline |
| isStore() const | BaseDynInst< Impl > | inline |
| isStoreConditional() const | BaseDynInst< Impl > | inline |
| IsStrictlyOrdered enum value | BaseDynInst< Impl > | protected |
| Issued enum value | BaseDynInst< Impl > | protected |
| isSyscall() const | BaseDynInst< Impl > | inline |
| isTempSerializeAfter() | BaseDynInst< Impl > | inline |
| isTempSerializeBefore() | BaseDynInst< Impl > | inline |
| isThreadSync() const | BaseDynInst< Impl > | inline |
| isTranslationDelayed() const | BaseDynInst< Impl > | inline |
| isUncondCtrl() const | BaseDynInst< Impl > | inline |
| isUnverifiable() const | BaseDynInst< Impl > | inline |
| isWriteBarrier() const | BaseDynInst< Impl > | inline |
| ListIt typedef | BaseDynInst< Impl > | |
| lqIdx | BaseDynInst< Impl > | |
| LsqEntry enum value | BaseDynInst< Impl > | protected |
| MachInst typedef | BaseO3DynInst< Impl > | |
| macroop | BaseDynInst< Impl > | |
| markSrcRegReady() | BaseDynInst< Impl > | |
| markSrcRegReady(RegIndex src_idx) | BaseDynInst< Impl > | |
| masterId() const | BaseDynInst< Impl > | inline |
| MaxFlags enum value | BaseDynInst< Impl > | protected |
| MaxInstDestRegs enum value | BaseO3DynInst< Impl > | |
| MaxInstSrcRegs enum value | BaseO3DynInst< Impl > | |
| memAccess() | BaseO3DynInst< Impl > | inline |
| memData | BaseDynInst< Impl > | |
| MemOpDone enum value | BaseDynInst< Impl > | protected |
| memOpDone() const | BaseDynInst< Impl > | inline |
| memOpDone(bool f) | BaseDynInst< Impl > | inline |
| memReqFlags | BaseDynInst< Impl > | |
| microPC() const | BaseDynInst< Impl > | inline |
| MiscReg typedef | BaseO3DynInst< Impl > | |
| mispredicted() | BaseDynInst< Impl > | inline |
| mwait(PacketPtr pkt) | BaseDynInst< Impl > | inlinevirtual |
| mwaitAtomic(ThreadContext *tc) | BaseDynInst< Impl > | inlinevirtual |
| nextInstAddr() const | BaseDynInst< Impl > | inline |
| numCCDestRegs() const | BaseDynInst< Impl > | inline |
| numDestRegs() const | BaseDynInst< Impl > | inline |
| numFPDestRegs() const | BaseDynInst< Impl > | inline |
| numIntDestRegs() const | BaseDynInst< Impl > | inline |
| numSrcRegs() const | BaseDynInst< Impl > | inline |
| NumStatus enum value | BaseDynInst< Impl > | protected |
| O3CPU typedef | BaseO3DynInst< Impl > | |
| opClass() const | BaseDynInst< Impl > | inline |
| pc | BaseDynInst< Impl > | protected |
| pcState() const | BaseDynInst< Impl > | inlinevirtual |
| pcState(const TheISA::PCState &val) | BaseDynInst< Impl > | inlinevirtual |
| PCState typedef | ExecContext | |
| physEffAddrHigh | BaseDynInst< Impl > | |
| physEffAddrLow | BaseDynInst< Impl > | |
| popResult(T &t) | BaseDynInst< Impl > | inline |
| possibleLoadViolation() const | BaseDynInst< Impl > | inline |
| possibleLoadViolation(bool f) | BaseDynInst< Impl > | inline |
| PossibleLoadViolation enum value | BaseDynInst< Impl > | protected |
| Predicate enum value | BaseDynInst< Impl > | protected |
| predInstAddr() | BaseDynInst< Impl > | inline |
| predMicroPC() | BaseDynInst< Impl > | inline |
| predNextInstAddr() | BaseDynInst< Impl > | inline |
| predPC | BaseDynInst< Impl > | |
| PredTaken enum value | BaseDynInst< Impl > | protected |
| prevDestRegIdx(int idx) const | BaseDynInst< Impl > | inline |
| readCCRegOperand(const StaticInst *si, int idx) | BaseO3DynInst< Impl > | inlinevirtual |
| readFloatRegOperand(const StaticInst *si, int idx) | BaseO3DynInst< Impl > | inlinevirtual |
| readFloatRegOperandBits(const StaticInst *si, int idx) | BaseO3DynInst< Impl > | inlinevirtual |
| readIntRegOperand(const StaticInst *si, int idx) | BaseO3DynInst< Impl > | inlinevirtual |
| readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags) | ExecContext | inlinevirtual |
| readMiscReg(int misc_reg) | BaseO3DynInst< Impl > | inlinevirtual |
| readMiscRegOperand(const StaticInst *si, int idx) | BaseO3DynInst< Impl > | inlinevirtual |
| readPredicate() | BaseDynInst< Impl > | inlinevirtual |
| readPredTaken() | BaseDynInst< Impl > | inline |
| readPredTarg() | BaseDynInst< Impl > | inline |
| readRegOtherThread(int misc_reg, ThreadID tid) | BaseO3DynInst< Impl > | inlinevirtual |
| readResult(T &t) | BaseDynInst< Impl > | inline |
| readStCondFailures() const | BaseDynInst< Impl > | inlinevirtual |
| readyRegs | BaseDynInst< Impl > | |
| readyToCommit() const | BaseDynInst< Impl > | inline |
| readyToIssue() const | BaseDynInst< Impl > | inline |
| recordResult(bool f) | BaseDynInst< Impl > | inline |
| RecordResult enum value | BaseDynInst< Impl > | protected |
| RecoverInst enum value | BaseDynInst< Impl > | protected |
| RefCounted() | RefCounted | inline |
| RegIndex typedef | BaseO3DynInst< Impl > | |
| removeInLSQ() | BaseDynInst< Impl > | inline |
| renamedDestRegIdx(int idx) const | BaseDynInst< Impl > | inline |
| renameDestReg(int idx, PhysRegIndex renamed_dest, PhysRegIndex previous_rename) | BaseDynInst< Impl > | inline |
| renamedSrcRegIdx(int idx) const | BaseDynInst< Impl > | inline |
| renameSrcReg(int idx, PhysRegIndex renamed_src) | BaseDynInst< Impl > | inline |
| ReqMade enum value | BaseDynInst< Impl > | protected |
| reqToVerify | BaseDynInst< Impl > | |
| ResultReady enum value | BaseDynInst< Impl > | protected |
| RobEntry enum value | BaseDynInst< Impl > | protected |
| savedReq | BaseDynInst< Impl > | |
| savedSreqHigh | BaseDynInst< Impl > | |
| savedSreqLow | BaseDynInst< Impl > | |
| seqNum | BaseDynInst< Impl > | |
| SerializeAfter enum value | BaseDynInst< Impl > | protected |
| SerializeBefore enum value | BaseDynInst< Impl > | protected |
| SerializeHandled enum value | BaseDynInst< Impl > | protected |
| setASID(short addr_space_id) | BaseDynInst< Impl > | inline |
| setAtCommit() | BaseDynInst< Impl > | inline |
| setCanCommit() | BaseDynInst< Impl > | inline |
| setCanIssue() | BaseDynInst< Impl > | inline |
| setCCRegOperand(const StaticInst *si, int idx, CCReg val) | BaseO3DynInst< Impl > | inlinevirtual |
| setCommitted() | BaseDynInst< Impl > | inline |
| setCompleted() | BaseDynInst< Impl > | inline |
| setEA(Addr ea) | BaseDynInst< Impl > | inlinevirtual |
| setExecuted() | BaseDynInst< Impl > | inline |
| setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) | BaseO3DynInst< Impl > | inlinevirtual |
| setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) | BaseO3DynInst< Impl > | inlinevirtual |
| setInIQ() | BaseDynInst< Impl > | inline |
| setInLSQ() | BaseDynInst< Impl > | inline |
| setInROB() | BaseDynInst< Impl > | inline |
| setInstListIt(ListIt _instListIt) | BaseDynInst< Impl > | inline |
| setIntRegOperand(const StaticInst *si, int idx, IntReg val) | BaseO3DynInst< Impl > | inlinevirtual |
| setIssued() | BaseDynInst< Impl > | inline |
| setMiscReg(int misc_reg, const MiscReg &val) | BaseO3DynInst< Impl > | inlinevirtual |
| setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) | BaseO3DynInst< Impl > | inlinevirtual |
| setPredicate(bool val) | BaseDynInst< Impl > | inlinevirtual |
| setPredTaken(bool predicted_taken) | BaseDynInst< Impl > | inline |
| setPredTarg(const TheISA::PCState &_predPC) | BaseDynInst< Impl > | inline |
| setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) | BaseO3DynInst< Impl > | inlinevirtual |
| setResult(T t) | BaseDynInst< Impl > | inline |
| setResultReady() | BaseDynInst< Impl > | inline |
| setSerializeAfter() | BaseDynInst< Impl > | inline |
| setSerializeBefore() | BaseDynInst< Impl > | inline |
| setSerializeHandled() | BaseDynInst< Impl > | inline |
| setSquashed() | BaseDynInst< Impl > | inline |
| setSquashedInIQ() | BaseDynInst< Impl > | inline |
| setSquashedInLSQ() | BaseDynInst< Impl > | inline |
| setSquashedInROB() | BaseDynInst< Impl > | inline |
| setStCondFailures(unsigned int sc_failures) | BaseDynInst< Impl > | inlinevirtual |
| setThreadState(ImplState *state) | BaseDynInst< Impl > | inline |
| setTid(ThreadID tid) | BaseDynInst< Impl > | inline |
| simPalCheck(int palFunc) | BaseO3DynInst< Impl > | virtual |
| socketId() const | BaseDynInst< Impl > | inline |
| splitRequest(RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh) | BaseDynInst< Impl > | inline |
| sqIdx | BaseDynInst< Impl > | |
| Squashed enum value | BaseDynInst< Impl > | protected |
| SquashedInIQ enum value | BaseDynInst< Impl > | protected |
| SquashedInLSQ enum value | BaseDynInst< Impl > | protected |
| SquashedInROB enum value | BaseDynInst< Impl > | protected |
| srcRegIdx(int i) const | BaseDynInst< Impl > | inline |
| staticInst | BaseDynInst< Impl > | |
| Status enum name | BaseDynInst< Impl > | protected |
| status | BaseDynInst< Impl > | protected |
| strictlyOrdered() const | BaseDynInst< Impl > | inline |
| syscall(int64_t callnum, Fault *fault) | BaseO3DynInst< Impl > | virtual |
| tcBase() | BaseDynInst< Impl > | inlinevirtual |
| thread | BaseDynInst< Impl > | |
| threadNumber | BaseDynInst< Impl > | |
| ThreadsyncWait enum value | BaseDynInst< Impl > | protected |
| traceData | BaseDynInst< Impl > | |
| translationCompleted() const | BaseDynInst< Impl > | inline |
| translationCompleted(bool f) | BaseDynInst< Impl > | inline |
| TranslationCompleted enum value | BaseDynInst< Impl > | protected |
| TranslationStarted enum value | BaseDynInst< Impl > | protected |
| translationStarted() const | BaseDynInst< Impl > | inline |
| translationStarted(bool f) | BaseDynInst< Impl > | inline |
| trap(const Fault &fault) | BaseO3DynInst< Impl > | |
| updateMiscRegs() | BaseO3DynInst< Impl > | inline |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) | BaseDynInst< Impl > | |
| ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res)=0 | ExecContext | pure virtual |
| ~BaseDynInst() | BaseDynInst< Impl > | |
| ~BaseO3DynInst() | BaseO3DynInst< Impl > | |
| ~RefCounted() | RefCounted | inlinevirtual |
