| _currPwrState | ClockedObject | protected |
| _params | SimObject | protected |
| _system | AbstractMemory | protected |
| AbstractMemory(const Params *p) | AbstractMemory | |
| access(PacketPtr pkt) | AbstractMemory | |
| accessAndRespond(PacketPtr pkt, Tick static_latency) | DRAMCtrl | private |
| activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row) | DRAMCtrl | private |
| activationLimit | DRAMCtrl | private |
| activeRank | DRAMCtrl | private |
| addLockedAddr(LockedAddr addr) | AbstractMemory | inline |
| addrMapping | DRAMCtrl | private |
| addToReadQueue(PacketPtr pkt, unsigned int pktCount) | DRAMCtrl | private |
| addToWriteQueue(PacketPtr pkt, unsigned int pktCount) | DRAMCtrl | private |
| allRanksDrained() const | DRAMCtrl | |
| avgBusLat | DRAMCtrl | private |
| avgGap | DRAMCtrl | private |
| avgMemAccLat | DRAMCtrl | private |
| avgQLat | DRAMCtrl | private |
| avgRdBW | DRAMCtrl | private |
| avgRdBWSys | DRAMCtrl | private |
| avgRdQLen | DRAMCtrl | private |
| avgWrBW | DRAMCtrl | private |
| avgWrBWSys | DRAMCtrl | private |
| avgWrQLen | DRAMCtrl | private |
| backendLatency | DRAMCtrl | private |
| bankGroupArch | DRAMCtrl | private |
| bankGroupsPerRank | DRAMCtrl | private |
| banksPerRank | DRAMCtrl | private |
| burstAlign(Addr addr) const | DRAMCtrl | inlineprivate |
| burstLength | DRAMCtrl | private |
| burstSize | DRAMCtrl | private |
| busBusyUntil | DRAMCtrl | private |
| busState | DRAMCtrl | private |
| BusState enum name | DRAMCtrl | private |
| busStateNext | DRAMCtrl | private |
| busUtil | DRAMCtrl | private |
| busUtilRead | DRAMCtrl | private |
| busUtilWrite | DRAMCtrl | private |
| bwInstRead | AbstractMemory | protected |
| bwRead | AbstractMemory | protected |
| bwTotal | AbstractMemory | protected |
| bwWrite | AbstractMemory | protected |
| bytesInstRead | AbstractMemory | protected |
| bytesPerActivate | DRAMCtrl | private |
| bytesRead | AbstractMemory | protected |
| bytesReadDRAM | DRAMCtrl | private |
| bytesReadSys | DRAMCtrl | private |
| bytesReadWrQ | DRAMCtrl | private |
| bytesWritten | DRAMCtrl | private |
| bytesWrittenSys | DRAMCtrl | private |
| channels | DRAMCtrl | private |
| checkLockedAddrList(PacketPtr pkt) | AbstractMemory | protected |
| chooseNext(std::deque< DRAMPacket * > &queue, Tick extra_col_delay) | DRAMCtrl | private |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| columnsPerRowBuffer | DRAMCtrl | private |
| columnsPerStripe | DRAMCtrl | private |
| computeStats() | ClockedObject | |
| confTableReported | AbstractMemory | protected |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, bool isRead) | DRAMCtrl | private |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| deviceBusWidth | DRAMCtrl | private |
| deviceRowBufferSize | DRAMCtrl | private |
| deviceSize | DRAMCtrl | private |
| devicesPerRank | DRAMCtrl | private |
| doDRAMAccess(DRAMPacket *dram_pkt) | DRAMCtrl | private |
| drain() override | DRAMCtrl | virtual |
| Drainable() | Drainable | protected |
| drainResume() override | DRAMCtrl | virtual |
| drainState() const | Drainable | inline |
| DRAMCtrl(const DRAMCtrlParams *p) | DRAMCtrl | |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| find(const char *name) | SimObject | static |
| frequency() const | Clocked | inline |
| frontendLatency | DRAMCtrl | private |
| functionalAccess(PacketPtr pkt) | AbstractMemory | |
| getAddrRange() const | AbstractMemory | |
| getLockedAddrList() const | AbstractMemory | inline |
| getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) | MemObject | virtual |
| getProbeManager() | SimObject | |
| getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) override | DRAMCtrl | virtual |
| inAddrMap | AbstractMemory | protected |
| init() override | DRAMCtrl | virtual |
| initState() | SimObject | virtual |
| isConfReported() const | AbstractMemory | inline |
| isInAddrMap() const | AbstractMemory | inline |
| isInWriteQueue | DRAMCtrl | private |
| isKvmMap() const | AbstractMemory | inline |
| isNull() const | AbstractMemory | inline |
| isTimingMode | DRAMCtrl | private |
| kvmMap | AbstractMemory | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lockedAddrList | AbstractMemory | protected |
| maxAccessesPerRow | DRAMCtrl | private |
| memInvalidate() | SimObject | inlinevirtual |
| MemObject(const Params *params) | MemObject | |
| memSchedPolicy | DRAMCtrl | private |
| memWriteback() | SimObject | inlinevirtual |
| mergedWrBursts | DRAMCtrl | private |
| minBankPrep(const std::deque< DRAMPacket * > &queue, Tick min_col_at) const | DRAMCtrl | private |
| minWritesPerSwitch | DRAMCtrl | private |
| name() const | SimObject | inlinevirtual |
| neitherReadNorWrite | DRAMCtrl | private |
| nextCycle() const | Clocked | inline |
| nextReqEvent | DRAMCtrl | private |
| nextReqTime | DRAMCtrl | private |
| notifyFork() | Drainable | inlinevirtual |
| numOther | AbstractMemory | protected |
| numPwrStateTransitions | ClockedObject | protected |
| numRdRetry | DRAMCtrl | private |
| numReads | AbstractMemory | protected |
| numWrites | AbstractMemory | protected |
| numWrRetry | DRAMCtrl | private |
| MemObject::operator=(Clocked &)=delete | Clocked | protected |
| pageHitRate | DRAMCtrl | private |
| pageMgmt | DRAMCtrl | private |
| Params typedef | AbstractMemory | |
| params() const | AbstractMemory | inline |
| peakBW | DRAMCtrl | private |
| pendingDelete | DRAMCtrl | private |
| perBankRdBursts | DRAMCtrl | private |
| perBankWrBursts | DRAMCtrl | private |
| pmemAddr | AbstractMemory | protected |
| port | DRAMCtrl | private |
| PowerState enum name | DRAMCtrl | private |
| prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_at, bool trace=true) | DRAMCtrl | private |
| prevArrival | DRAMCtrl | private |
| printQs() const | DRAMCtrl | private |
| processNextReqEvent() | DRAMCtrl | private |
| processRespondEvent() | DRAMCtrl | private |
| prvEvalTick | ClockedObject | protected |
| PWR_ACT enum value | DRAMCtrl | private |
| PWR_ACT_PDN enum value | DRAMCtrl | private |
| PWR_IDLE enum value | DRAMCtrl | private |
| PWR_PRE_PDN enum value | DRAMCtrl | private |
| PWR_REF enum value | DRAMCtrl | private |
| PWR_SREF enum value | DRAMCtrl | private |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| range | AbstractMemory | protected |
| ranks | DRAMCtrl | private |
| ranksPerChannel | DRAMCtrl | private |
| rdPerTurnAround | DRAMCtrl | private |
| rdQLenPdf | DRAMCtrl | private |
| READ enum value | DRAMCtrl | private |
| readBufferSize | DRAMCtrl | private |
| readBursts | DRAMCtrl | private |
| readPktSize | DRAMCtrl | private |
| readQueue | DRAMCtrl | private |
| readQueueFull(unsigned int pktCount) const | DRAMCtrl | private |
| readReqs | DRAMCtrl | private |
| readRowHitRate | DRAMCtrl | private |
| readRowHits | DRAMCtrl | private |
| readsThisTime | DRAMCtrl | private |
| recvAtomic(PacketPtr pkt) | DRAMCtrl | protected |
| recvFunctional(PacketPtr pkt) | DRAMCtrl | protected |
| recvTimingReq(PacketPtr pkt) | DRAMCtrl | protected |
| REF_DRAIN enum value | DRAMCtrl | private |
| REF_IDLE enum value | DRAMCtrl | private |
| REF_PD_EXIT enum value | DRAMCtrl | private |
| REF_PRE enum value | DRAMCtrl | private |
| REF_RUN enum value | DRAMCtrl | private |
| REF_SREF_EXIT enum value | DRAMCtrl | private |
| REF_START enum value | DRAMCtrl | private |
| RefreshState enum name | DRAMCtrl | private |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() override | DRAMCtrl | virtual |
| reorderQueue(std::deque< DRAMPacket * > &queue, Tick extra_col_delay) | DRAMCtrl | private |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | SimObject | virtual |
| respondEvent | DRAMCtrl | private |
| respQueue | DRAMCtrl | private |
| retryRdReq | DRAMCtrl | private |
| retryWrReq | DRAMCtrl | private |
| rowBufferSize | DRAMCtrl | private |
| rowsPerBank | DRAMCtrl | private |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| servicedByWrQ | DRAMCtrl | private |
| setBackingStore(uint8_t *pmem_addr) | AbstractMemory | |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| size() const | AbstractMemory | inline |
| sortTime(const Command &cmd, const Command &cmd_next) | DRAMCtrl | inlineprivatestatic |
| start() const | AbstractMemory | inline |
| startup() override | DRAMCtrl | virtual |
| system() const | AbstractMemory | inline |
| system(System *sys) | AbstractMemory | inline |
| tBURST | DRAMCtrl | private |
| tCCD_L | DRAMCtrl | private |
| tCK | DRAMCtrl | private |
| tCL | DRAMCtrl | private |
| tCS | DRAMCtrl | private |
| ticksToCycles(Tick t) const | Clocked | inline |
| timeStampOffset | DRAMCtrl | private |
| totBusLat | DRAMCtrl | private |
| totGap | DRAMCtrl | private |
| totMemAccLat | DRAMCtrl | private |
| totQLat | DRAMCtrl | private |
| trackLoadLocked(PacketPtr pkt) | AbstractMemory | protected |
| tRAS | DRAMCtrl | private |
| tRCD | DRAMCtrl | private |
| tREFI | DRAMCtrl | private |
| tRFC | DRAMCtrl | private |
| tRP | DRAMCtrl | private |
| tRRD | DRAMCtrl | private |
| tRRD_L | DRAMCtrl | private |
| tRTP | DRAMCtrl | private |
| tRTW | DRAMCtrl | private |
| tWR | DRAMCtrl | private |
| tWTR | DRAMCtrl | private |
| tXAW | DRAMCtrl | private |
| tXP | DRAMCtrl | private |
| tXS | DRAMCtrl | private |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateClockPeriod() const | Clocked | inline |
| updatePowerStats(Rank &rank_ref) | DRAMCtrl | private |
| voltage() const | Clocked | inline |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| WRITE enum value | DRAMCtrl | private |
| writeBufferSize | DRAMCtrl | private |
| writeBursts | DRAMCtrl | private |
| writeHighThreshold | DRAMCtrl | private |
| writeLowThreshold | DRAMCtrl | private |
| writeOK(PacketPtr pkt) | AbstractMemory | inlineprotected |
| writePktSize | DRAMCtrl | private |
| writeQueue | DRAMCtrl | private |
| writeQueueFull(unsigned int pktCount) const | DRAMCtrl | private |
| writeReqs | DRAMCtrl | private |
| writeRowHitRate | DRAMCtrl | private |
| writeRowHits | DRAMCtrl | private |
| writesThisTime | DRAMCtrl | private |
| wrPerTurnAround | DRAMCtrl | private |
| wrQLenPdf | DRAMCtrl | private |
| ~AbstractMemory() | AbstractMemory | inlinevirtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
