gem5
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
HsailISA::BrnInstBase< TargetType > Member List

This is the complete list of members for HsailISA::BrnInstBase< TargetType >, including all inherited members.

_flagsGPUStaticInstprotected
_instAddrGPUStaticInstprotected
_instNumGPUStaticInstprotected
_ipdInstNumGPUStaticInstprotected
BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)HsailISA::BrnInstBase< TargetType >inline
completeAcc(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
disassemble()GPUStaticInst
disassemblyGPUStaticInstprotected
dynamic_id_countGPUStaticInststatic
execAtomic(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
execAtomicAcq(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
execLdAcq(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
execSt(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
execute(GPUDynInstPtr gpuDynInst) overrideHsailISA::BrnInstBase< TargetType >virtual
executed_asGPUStaticInst
generateDisassembly() overrideHsailISA::BrnInstBase< TargetType >virtual
getNumOperands() overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
getOperandSize(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
getTargetPc() overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
GPUStaticInst(const std::string &opcode)GPUStaticInst
hsailCodeHsailISA::HsailGPUStaticInstprotected
HsailGPUStaticInst(const BrigObject *obj, const std::string &opcode)HsailISA::HsailGPUStaticInst
initiateAcc(GPUDynInstPtr gpuDynInst)GPUStaticInstinlinevirtual
instAddr(int inst_addr)GPUStaticInstinline
instAddr() const GPUStaticInstinline
instNum(int num)GPUStaticInstinline
instNum()GPUStaticInstinline
instSize() const overrideHsailISA::HsailGPUStaticInstinlinevirtual
ipdInstNum(int num)GPUStaticInstinline
ipdInstNum() const GPUStaticInstinline
isAcquire() const GPUStaticInstinline
isAcquireRelease() const GPUStaticInstinline
isALU() const GPUStaticInstinline
isArgLoad() const GPUStaticInstinline
isArgSeg() const GPUStaticInstinline
isAtomic() const GPUStaticInstinline
isAtomicAdd() const GPUStaticInstinline
isAtomicAnd() const GPUStaticInstinline
isAtomicCAS() const GPUStaticInstinline
isAtomicDec() const GPUStaticInstinline
isAtomicExch() const GPUStaticInstinline
isAtomicInc() const GPUStaticInstinline
isAtomicMax() const GPUStaticInstinline
isAtomicMin() const GPUStaticInstinline
isAtomicNoRet() const GPUStaticInstinline
isAtomicOr() const GPUStaticInstinline
isAtomicRet() const GPUStaticInstinline
isAtomicSub() const GPUStaticInstinline
isAtomicXor() const GPUStaticInstinline
isBarrier() const GPUStaticInstinline
isBranch() const GPUStaticInstinline
isCondRegister(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
isDeviceScope() const GPUStaticInstinline
isDstOperand(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
isFlat() const GPUStaticInstinline
isGloballyCoherent() const GPUStaticInstinline
isGlobalMem() const GPUStaticInstinline
isGlobalSeg() const GPUStaticInstinline
isGroupSeg() const GPUStaticInstinline
isKernArgSeg() const GPUStaticInstinline
isLoad() const GPUStaticInstinline
isLocalMem() const GPUStaticInstinline
isMemFence() const GPUStaticInstinline
isMemRef() const GPUStaticInstinline
isNoOrder() const GPUStaticInstinline
isNop() const GPUStaticInstinline
isNoScope() const GPUStaticInstinline
isPrivateSeg() const GPUStaticInstinline
isReadOnlySeg() const GPUStaticInstinline
isRelaxedOrder() const GPUStaticInstinline
isRelease() const GPUStaticInstinline
isReturn() const GPUStaticInstinline
isScalar() const GPUStaticInstinline
isScalarRegister(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
isSpecialOp() const GPUStaticInstinline
isSpillSeg() const GPUStaticInstinline
isSrcOperand(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
isStore() const GPUStaticInstinline
isSystemCoherent() const GPUStaticInstinline
isSystemScope() const GPUStaticInstinline
isUnconditionalJump() const GPUStaticInstinline
isValid() const overrideHsailISA::HsailGPUStaticInstinlinevirtual
isVectorRegister(int operandIndex) overrideHsailISA::BrnInstBase< TargetType >inlinevirtual
isWaitcnt() const GPUStaticInstinline
isWavefrontScope() const GPUStaticInstinline
isWorkgroupScope() const GPUStaticInstinline
isWorkitemScope() const GPUStaticInstinline
nextInstAddr() const GPUStaticInstinline
numDstRegOperands()=0GPUStaticInstpure virtual
numSrcRegOperands()=0GPUStaticInstpure virtual
opcodeGPUStaticInstprotected
readsSCC() const GPUStaticInstinline
readsVCC() const GPUStaticInstinline
setFlag(Flags flag)GPUStaticInstinline
targetHsailISA::BrnInstBase< TargetType >
widthHsailISA::BrnInstBase< TargetType >
writesSCC() const GPUStaticInstinline
writesVCC() const GPUStaticInstinline
Generated on Fri Jun 9 2017 13:04:31 for gem5 by doxygen 1.8.6