| _busAddr | PciDevice | protected |
| _currPwrState | ClockedObject | protected |
| _params | SimObject | protected |
| active | IdeController | private |
| BARAddrs | PciDevice | protected |
| BARSize | PciDevice | protected |
| BitUnion8(BMIStatusReg) Bitfield< 6 > dmaCap0 | IdeController | private |
| bmEnabled | IdeController | private |
| bmiAddr | IdeController | private |
| bmiSize | IdeController | private |
| busAddr() const | PciDevice | inline |
| cacheBlockSize() const | DmaDevice | inline |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| computeStats() | ClockedObject | |
| config | PciDevice | protected |
| configDelay | PciDevice | protected |
| ctrlOffset | IdeController | private |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| deviceTiming | IdeController | private |
| dispatchAccess(PacketPtr pkt, bool read) | IdeController | private |
| dmaCap1 | IdeController | private |
| DmaDevice(const Params *p) | DmaDevice | |
| dmaError | IdeController | private |
| dmaPending() const | DmaDevice | inline |
| dmaPort | DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | DmaDevice | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| EndBitUnion(BMIStatusReg) BitUnion8(BMICommandReg) Bitfield< 3 > rw | IdeController | private |
| EndBitUnion(BMICommandReg) struct Channel | IdeController | inlineprivate |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| find(const char *name) | SimObject | static |
| frequency() const | Clocked | inline |
| getAddrRanges() const override | PciDevice | virtual |
| getBAR(Addr addr) | PciDevice | inlineprotected |
| getBAR(Addr addr, int &bar, Addr &offs) | PciDevice | inlineprotected |
| getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) override | DmaDevice | virtual |
| getProbeManager() | SimObject | |
| getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | PioDevice | virtual |
| hostInterface | PciDevice | protected |
| ideConfig | IdeController | private |
| IdeController(Params *p) | IdeController | |
| init() override | DmaDevice | virtual |
| initState() | SimObject | virtual |
| interruptLine() const | PciDevice | inline |
| intrClear() | PciDevice | inline |
| intrPost() | IdeController | |
| intStatus | IdeController | private |
| ioEnabled | IdeController | private |
| ioShift | IdeController | private |
| isBAR(Addr addr, int bar) const | PciDevice | inlineprotected |
| isDiskSelected(IdeDisk *diskPtr) | IdeController | |
| legacyIO | PciDevice | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| memInvalidate() | SimObject | inlinevirtual |
| MemObject(const Params *params) | MemObject | |
| memWriteback() | SimObject | inlinevirtual |
| msicap | PciDevice | protected |
| MSICAP_BASE | PciDevice | protected |
| msix_pba | PciDevice | protected |
| MSIX_PBA_END | PciDevice | protected |
| MSIX_PBA_OFFSET | PciDevice | protected |
| msix_table | PciDevice | protected |
| MSIX_TABLE_END | PciDevice | protected |
| MSIX_TABLE_OFFSET | PciDevice | protected |
| msixcap | PciDevice | protected |
| MSIXCAP_BASE | PciDevice | protected |
| MSIXCAP_ID_OFFSET | PciDevice | protected |
| MSIXCAP_MPBA_OFFSET | PciDevice | protected |
| MSIXCAP_MTAB_OFFSET | PciDevice | protected |
| MSIXCAP_MXC_OFFSET | PciDevice | protected |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| numPwrStateTransitions | ClockedObject | protected |
| operator=(Clocked &)=delete | Clocked | protected |
| Params typedef | IdeController | |
| params() const | IdeController | inline |
| PciDevice(const PciDeviceParams *params) | PciDevice | |
| pciToDma(Addr pci_addr) const | PciDevice | inline |
| pioDelay | PciDevice | protected |
| PioDevice(const Params *p) | PioDevice | |
| pioPort | PioDevice | protected |
| pmcap | PciDevice | protected |
| PMCAP_BASE | PciDevice | protected |
| PMCAP_ID_OFFSET | PciDevice | protected |
| PMCAP_PC_OFFSET | PciDevice | protected |
| PMCAP_PMCS_OFFSET | PciDevice | protected |
| primary | IdeController | private |
| primaryTiming | IdeController | private |
| prvEvalTick | ClockedObject | protected |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| pxcap | PciDevice | protected |
| PXCAP_BASE | PciDevice | protected |
| read(PacketPtr pkt) override | IdeController | virtual |
| readConfig(PacketPtr pkt) override | IdeController | virtual |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() override | ClockedObject | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | SimObject | virtual |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| secondary | IdeController | private |
| secondaryTiming | IdeController | private |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | IdeController | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| setDmaComplete(IdeDisk *disk) | IdeController | |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| startStop | IdeController | private |
| startup() | SimObject | virtual |
| sys | PioDevice | protected |
| ticksToCycles(Tick t) const | Clocked | inline |
| udmaControl | IdeController | private |
| udmaTiming | IdeController | private |
| unserialize(CheckpointIn &cp) override | IdeController | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateClockPeriod() const | Clocked | inline |
| voltage() const | Clocked | inline |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| write(PacketPtr pkt) override | IdeController | virtual |
| writeConfig(PacketPtr pkt) override | IdeController | virtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~DmaDevice() | DmaDevice | inlinevirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~PioDevice() | PioDevice | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
