gem5
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
PowerISA::BranchRegCond Member List

This is the complete list of members for PowerISA::BranchRegCond, including all inherited members.

_destRegIdxStaticInstprotected
_numCCDestRegsStaticInstprotected
_numDestRegsStaticInstprotected
_numFPDestRegsStaticInstprotected
_numIntDestRegsStaticInstprotected
_numSrcRegsStaticInstprotected
_opClassStaticInstprotected
_srcRegIdxStaticInstprotected
advancePC(PowerISA::PCState &pcState) const PowerISA::PowerStaticInstinlineprotected
StaticInst::advancePC(TheISA::PCState &pcState) const =0StaticInstpure virtual
biPowerISA::BranchCondprotected
boPowerISA::BranchCondprotected
BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)PowerISA::BranchCondinlineprotected
BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)PowerISA::BranchRegCondinlineprotected
branchTarget(ThreadContext *tc) const PowerISA::BranchRegCondprotectedvirtual
PowerISA::BranchCond::branchTarget(const TheISA::PCState &pc) const StaticInstvirtual
cachedDisassemblyStaticInstmutableprotected
cachedPCPowerISA::PCDependentDisassemblymutableprotected
cachedSymtabPowerISA::PCDependentDisassemblymutableprotected
completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
condOk(uint32_t cr) const PowerISA::BranchCondinlineprotected
ctrOk(uint32_t &ctr) const PowerISA::BranchCondinlineprotected
decref()RefCountedinline
destRegIdx(int i) const StaticInstinline
disassemble(Addr pc, const SymbolTable *symtab) const PowerISA::PCDependentDisassemblyprotectedvirtual
eaComp(ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
eaCompInst() const StaticInstinlinevirtual
execute(ExecContext *xc, Trace::InstRecord *traceData) const =0StaticInstpure virtual
ExtMachInst typedefStaticInst
fetchMicroop(MicroPC upc) const StaticInstvirtual
flagsStaticInstprotected
generateDisassembly(Addr pc, const SymbolTable *symtab) const PowerISA::BranchRegCondprotectedvirtual
getName()StaticInstinline
hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const StaticInst
incref()RefCountedinline
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const PowerISA::PowerStaticInstinlineprotected
isCall() const StaticInstinline
isCC() const StaticInstinline
isCondCtrl() const StaticInstinline
isCondDelaySlot() const StaticInstinline
isControl() const StaticInstinline
isDataPrefetch() const StaticInstinline
isDelayedCommit() const StaticInstinline
isDirectCtrl() const StaticInstinline
isFirstMicroop() const StaticInstinline
isFloating() const StaticInstinline
isIndirectCtrl() const StaticInstinline
isInstPrefetch() const StaticInstinline
isInteger() const StaticInstinline
isIprAccess() const StaticInstinline
isLastMicroop() const StaticInstinline
isLoad() const StaticInstinline
isMacroop() const StaticInstinline
isMemBarrier() const StaticInstinline
isMemRef() const StaticInstinline
isMicroBranch() const StaticInstinline
isMicroop() const StaticInstinline
isNonSpeculative() const StaticInstinline
isNop() const StaticInstinline
isPrefetch() const StaticInstinline
isQuiesce() const StaticInstinline
isReturn() const StaticInstinline
isSerializeAfter() const StaticInstinline
isSerializeBefore() const StaticInstinline
isSerializing() const StaticInstinline
isSquashAfter() const StaticInstinline
isStore() const StaticInstinline
isStoreConditional() const StaticInstinline
isSyscall() const StaticInstinline
isThreadSync() const StaticInstinline
isUncondCtrl() const StaticInstinline
isUnverifiable() const StaticInstinline
isWriteBarrier() const StaticInstinline
machInstStaticInst
MaxInstDestRegs enum valueStaticInst
MaxInstSrcRegs enum valueStaticInst
memAccInst() const StaticInstinlinevirtual
mnemonicStaticInstprotected
nullStaticInstPtrStaticInststatic
numCCDestRegs() const StaticInstinline
numDestRegs() const StaticInstinline
numFPDestRegs() const StaticInstinline
numIntDestRegs() const StaticInstinline
numSrcRegs() const StaticInstinline
opClass() const StaticInstinline
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass)PowerISA::PCDependentDisassemblyinlineprotected
PowerStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)PowerISA::PowerStaticInstinlineprotected
printFlags(std::ostream &outs, const std::string &separator) const StaticInst
printReg(std::ostream &os, int reg) const PowerISA::PowerStaticInstprotected
RefCounted()RefCountedinline
RegIndex typedefStaticInst
setDelayedCommit()StaticInstinline
setFirstMicroop()StaticInstinline
setFlag(Flags f)StaticInstinline
setLastMicroop()StaticInstinline
srcRegIdx(int i) const StaticInstinline
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)StaticInstinlineprotected
~RefCounted()RefCountedinlinevirtual
~StaticInst()StaticInstvirtual
Generated on Fri Jun 9 2017 13:04:34 for gem5 by doxygen 1.8.6