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This is the complete list of members for RiscvISA::TLB, including all inherited members.
| _params | SimObject | protected |
| accesses | RiscvISA::TLB | protected |
| BaseTLB(const Params *p) | BaseTLB | inlineprotected |
| checkCacheability(RequestPtr &req) | RiscvISA::TLB | inlinestatic |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| currentSection() | Serializable | static |
| demapPage(Addr vaddr, uint64_t asn) override | RiscvISA::TLB | inlinevirtual |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| Execute enum value | BaseTLB | |
| finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const | RiscvISA::TLB | |
| find(const char *name) | SimObject | static |
| flushAll() override | RiscvISA::TLB | virtual |
| getEntry(unsigned) const | RiscvISA::TLB | |
| getMasterPort() | BaseTLB | inlinevirtual |
| getProbeManager() | SimObject | |
| getsize() const | RiscvISA::TLB | inline |
| hits | RiscvISA::TLB | protected |
| index(bool advance=true) | RiscvISA::TLB | |
| init() | SimObject | virtual |
| initState() | SimObject | virtual |
| insert(Addr vaddr, RiscvISA::PTE &pte) | RiscvISA::TLB | |
| insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages) | RiscvISA::TLB | |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lookup(Addr vpn, uint8_t asn) const | RiscvISA::TLB | protected |
| lookupTable | RiscvISA::TLB | protected |
| memInvalidate() | BaseTLB | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| misses | RiscvISA::TLB | protected |
| Mode enum name | BaseTLB | |
| name() const | SimObject | inlinevirtual |
| nextnlu() | RiscvISA::TLB | inlineprotected |
| nlu | RiscvISA::TLB | protected |
| notifyFork() | Drainable | inlinevirtual |
| PageTable typedef | RiscvISA::TLB | protected |
| Params typedef | RiscvISA::TLB | |
| params() const | SimObject | inline |
| probeEntry(Addr vpn, uint8_t) const | RiscvISA::TLB | |
| Read enum value | BaseTLB | |
| read_accesses | RiscvISA::TLB | mutableprotected |
| read_acv | RiscvISA::TLB | mutableprotected |
| read_hits | RiscvISA::TLB | mutableprotected |
| read_misses | RiscvISA::TLB | mutableprotected |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() override | RiscvISA::TLB | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetStats() | SimObject | virtual |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | RiscvISA::TLB | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| size | RiscvISA::TLB | protected |
| smallPages | RiscvISA::TLB | |
| startup() | SimObject | virtual |
| table | RiscvISA::TLB | protected |
| takeOverFrom(BaseTLB *otlb) override | RiscvISA::TLB | inlinevirtual |
| TLB(const Params *p) | RiscvISA::TLB | |
| translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) | RiscvISA::TLB | |
| translateData(RequestPtr req, ThreadContext *tc, bool write) | RiscvISA::TLB | private |
| translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) | RiscvISA::TLB | |
| translateInst(RequestPtr req, ThreadContext *tc) | RiscvISA::TLB | private |
| translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode) | RiscvISA::TLB | |
| unserialize(CheckpointIn &cp) override | RiscvISA::TLB | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| validVirtualAddress(Addr vaddr) | RiscvISA::TLB | static |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| Write enum value | BaseTLB | |
| write_accesses | RiscvISA::TLB | mutableprotected |
| write_acv | RiscvISA::TLB | mutableprotected |
| write_hits | RiscvISA::TLB | mutableprotected |
| write_misses | RiscvISA::TLB | mutableprotected |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
| ~TLB() | RiscvISA::TLB | virtual |