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ArmISA::BranchImmReg Member List

This is the complete list of members for ArmISA::BranchImmReg, including all inherited members.

_destRegIdxStaticInstprotected
_numCCDestRegsStaticInstprotected
_numDestRegsStaticInstprotected
_numFPDestRegsStaticInstprotected
_numIntDestRegsStaticInstprotected
_numSrcRegsStaticInstprotected
_opClassStaticInstprotected
_srcRegIdxStaticInstprotected
aarch64ArmISA::ArmStaticInstprotected
advancePC(PCState &pcState) const ArmISA::ArmStaticInstinlineprotected
StaticInst::advancePC(TheISA::PCState &pcState) const =0StaticInstpure virtual
advSIMDFPAccessTrap64(ExceptionLevel el) const ArmISA::ArmStaticInstprotected
annotateFault(ArmFault *fault)ArmISA::ArmStaticInstinlinevirtual
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)ArmISA::ArmStaticInstinlineprotected
BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, IntRegIndex _op1)ArmISA::BranchImmReginline
branchTarget(const TheISA::PCState &pc) const StaticInstvirtual
branchTarget(ThreadContext *tc) const StaticInstvirtual
cachedDisassemblyStaticInstmutableprotected
checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const ArmISA::ArmStaticInstprotected
checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const ArmISA::ArmStaticInstprotected
checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const ArmISA::ArmStaticInstprotected
completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
condCodeArmISA::PredOpprotected
cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)ArmISA::ArmStaticInstinlineprotectedstatic
decref()RefCountedinline
destRegIdx(int i) const StaticInstinline
disabledFault() const ArmISA::ArmStaticInstinlineprotected
disassemble(Addr pc, const SymbolTable *symtab=0) const StaticInstvirtual
eaComp(ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
eaCompInst() const StaticInstinlinevirtual
execute(ExecContext *xc, Trace::InstRecord *traceData) const =0StaticInstpure virtual
extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const ArmISA::ArmStaticInstprotected
ExtMachInst typedefStaticInst
fetchMicroop(MicroPC upc) const StaticInstvirtual
flagsStaticInstprotected
generateDisassembly(Addr pc, const SymbolTable *symtab) const ArmISA::ArmStaticInstprotectedvirtual
getName()StaticInstinline
getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const ArmISA::ArmStaticInstprotected
hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const StaticInst
immArmISA::BranchImmRegprotected
incref()RefCountedinline
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const StaticInstinlinevirtual
intWidthArmISA::ArmStaticInstprotected
isCall() const StaticInstinline
isCC() const StaticInstinline
isCondCtrl() const StaticInstinline
isCondDelaySlot() const StaticInstinline
isControl() const StaticInstinline
isDataPrefetch() const StaticInstinline
isDelayedCommit() const StaticInstinline
isDirectCtrl() const StaticInstinline
isFirstMicroop() const StaticInstinline
isFloating() const StaticInstinline
isIndirectCtrl() const StaticInstinline
isInstPrefetch() const StaticInstinline
isInteger() const StaticInstinline
isIprAccess() const StaticInstinline
isLastMicroop() const StaticInstinline
isLoad() const StaticInstinline
isMacroop() const StaticInstinline
isMemBarrier() const StaticInstinline
isMemRef() const StaticInstinline
isMicroBranch() const StaticInstinline
isMicroop() const StaticInstinline
isNonSpeculative() const StaticInstinline
isNop() const StaticInstinline
isPrefetch() const StaticInstinline
isQuiesce() const StaticInstinline
isReturn() const StaticInstinline
isSerializeAfter() const StaticInstinline
isSerializeBefore() const StaticInstinline
isSerializing() const StaticInstinline
isSquashAfter() const StaticInstinline
isStore() const StaticInstinline
isStoreConditional() const StaticInstinline
isSyscall() const StaticInstinline
isThreadSync() const StaticInstinline
isUncondCtrl() const StaticInstinline
isUnverifiable() const StaticInstinline
isWriteBarrier() const StaticInstinline
machInstStaticInst
MaxInstDestRegs enum valueStaticInst
MaxInstSrcRegs enum valueStaticInst
memAccInst() const StaticInstinlinevirtual
mnemonicStaticInstprotected
nullStaticInstPtrStaticInststatic
numCCDestRegs() const StaticInstinline
numDestRegs() const StaticInstinline
numFPDestRegs() const StaticInstinline
numIntDestRegs() const StaticInstinline
numSrcRegs() const StaticInstinline
op1ArmISA::BranchImmRegprotected
opClass() const StaticInstinline
PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)ArmISA::PredOpinlineprotected
printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const ArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm) const ArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const ArmISA::ArmStaticInstprotected
printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const ArmISA::ArmStaticInstprotected
printFlags(std::ostream &outs, const std::string &separator) const StaticInst
printMemSymbol(std::ostream &os, const SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const ArmISA::ArmStaticInstprotected
printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const ArmISA::ArmStaticInstprotected
printReg(std::ostream &os, int reg) const ArmISA::ArmStaticInstprotected
printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const ArmISA::ArmStaticInstprotected
printTarget(std::ostream &os, Addr target, const SymbolTable *symtab) const ArmISA::ArmStaticInstprotected
readPC(XC *xc)ArmISA::ArmStaticInstinlineprotectedstatic
RefCounted()RefCountedinline
RegIndex typedefStaticInst
satInt(int32_t &res, int64_t op, int width)ArmISA::ArmStaticInstinlineprotectedstatic
saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)ArmISA::ArmStaticInstinlineprotectedstatic
setAIWNextPC(XC *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
setDelayedCommit()StaticInstinline
setFirstMicroop()StaticInstinline
setFlag(Flags f)StaticInstinline
setIWNextPC(XC *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
setLastMicroop()StaticInstinline
setNextPC(XC *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const ArmISA::ArmStaticInstprotected
shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const ArmISA::ArmStaticInstprotected
shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const ArmISA::ArmStaticInstprotected
shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const ArmISA::ArmStaticInstprotected
shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const ArmISA::ArmStaticInstprotected
spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)ArmISA::ArmStaticInstinlineprotectedstatic
srcRegIdx(int i) const StaticInstinline
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)StaticInstinlineprotected
uSatInt(int32_t &res, int64_t op, int width)ArmISA::ArmStaticInstinlineprotectedstatic
uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)ArmISA::ArmStaticInstinlineprotectedstatic
~RefCounted()RefCountedinlinevirtual
~StaticInst()StaticInstvirtual
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