gem5
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Functions | |
int | prevPrime (int n) |
template<class T > | |
bool | isPrime (const T &n) |
template<class T > | |
T | leastSigBit (const T &n) |
template<class T > | |
bool | isPowerOf2 (const T &n) |
uint64_t | power (uint32_t n, uint32_t e) |
int | floorLog2 (unsigned x) |
int | floorLog2 (unsigned long x) |
int | floorLog2 (unsigned long long x) |
int | floorLog2 (int x) |
int | floorLog2 (long x) |
int | floorLog2 (long long x) |
template<class T > | |
int | ceilLog2 (const T &n) |
template<class T > | |
T | floorPow2 (const T &n) |
template<class T > | |
T | ceilPow2 (const T &n) |
template<class T , class U > | |
T | divCeil (const T &a, const U &b) |
template<class T , class U > | |
T | roundUp (const T &val, const U &align) |
template<class T , class U > | |
T | roundDown (const T &val, const U &align) |
bool | isHex (char c) |
bool | isOct (char c) |
bool | isDec (char c) |
int | hex2Int (char c) |
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Definition at line 174 of file intmath.hh.
References floorLog2().
Referenced by DRAMCtrl::addToReadQueue(), DRAMCtrl::addToWriteQueue(), ceilPow2(), DRAMCtrl::DRAMCtrl(), TimingExprUn::eval(), DirectoryMemory::init(), and DRAMCtrl::regStats().
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Definition at line 191 of file intmath.hh.
References ceilLog2().
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Definition at line 198 of file intmath.hh.
References ArmISA::b.
Referenced by DRAMCtrl::activateBank(), Process::allocateMem(), BaseXBar::calcPacketTiming(), DRAMCtrl::doDRAMAccess(), DRAMCtrl::Rank::flushCmdList(), DRAMPower::getDataRate(), DRAMPower::getTimingParams(), TrafficGen::parseConfig(), DRAMCtrl::Rank::powerDownSleep(), DRAMCtrl::prechargeBank(), DRAMCtrl::Rank::processRefreshEvent(), DRAMSim2::readComplete(), SerialLink::SerialLinkSlavePort::recvTimingReq(), DRAMCtrl::recvTimingReq(), SerialLink::SerialLinkMasterPort::recvTimingResp(), Clocked::resetClock(), DRAMCtrl::Rank::scheduleWakeUpEvent(), DRAMCtrl::startup(), ComputeUnit::startWavefront(), AtomicSimpleCPU::tick(), Clocked::ticksToCycles(), SerialLink::SerialLinkSlavePort::trySendTiming(), SerialLink::SerialLinkMasterPort::trySendTiming(), Clocked::update(), GpuDispatcher::write(), and DRAMSim2::writeComplete().
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Definition at line 100 of file intmath.hh.
Referenced by Histogram::add(), CheckTable::addCheck(), BankedArray::BankedArray(), BaseSetAssoc::BaseSetAssoc(), BlockBloomFilter::BlockBloomFilter(), BulkBloomFilter::BulkBloomFilter(), ceilLog2(), DefaultBTB::DefaultBTB(), DirectoryMemory::DirectoryMemory(), FALRU::FALRU(), floorLog2(), floorPow2(), IndirectPredictor::getSetIndex(), Gicv2m::Gicv2m(), H3BloomFilter::H3BloomFilter(), StackDistProbe::handleRequest(), CacheMemory::init(), MultiLevelPageTable< ISAOps >::initState(), LSB_CountingBloomFilter::LSB_CountingBloomFilter(), MultiBitSelBloomFilter::MultiBitSelBloomFilter(), MultiGrainBloomFilter::MultiGrainBloomFilter(), NonCountingBloomFilter::NonCountingBloomFilter(), StridePrefetcher::pcHash(), RubySystem::RubySystem(), BasePrefetcher::setCache(), and MultiLevelPageTable< ISAOps >::walk().
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Definition at line 116 of file intmath.hh.
References ULL.
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Definition at line 135 of file intmath.hh.
References ULL.
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Definition at line 152 of file intmath.hh.
References floorLog2().
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Definition at line 159 of file intmath.hh.
References floorLog2().
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Definition at line 166 of file intmath.hh.
References floorLog2().
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Definition at line 184 of file intmath.hh.
References floorLog2().
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Definition at line 240 of file intmath.hh.
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Definition at line 234 of file intmath.hh.
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Definition at line 220 of file intmath.hh.
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Definition at line 228 of file intmath.hh.
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Definition at line 73 of file intmath.hh.
References leastSigBit(), and ArmISA::n.
Referenced by BaseSetAssoc::BaseSetAssoc(), BiModeBP::BiModeBP(), ChunkGenerator::ChunkGenerator(), ComputeUnit::ComputeUnit(), DefaultBTB::DefaultBTB(), DRAMCtrl::DRAMCtrl(), FALRU::FALRU(), Gicv2m::Gicv2m(), IndirectPredictor::IndirectPredictor(), LocalBP::LocalBP(), MemFootprintProbe::MemFootprintProbe(), PageTableBase::PageTableBase(), PciDevice::PciDevice(), RubySystem::RubySystem(), StoreSet::StoreSet(), StridePrefetcher::StridePrefetcher(), TournamentBP::TournamentBP(), and StackDistCalc::updateTree().
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Definition at line 45 of file intmath.hh.
References ArmISA::i, and ArmISA::n.
Referenced by prevPrime().
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Definition at line 66 of file intmath.hh.
Referenced by isPowerOf2().
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Definition at line 79 of file intmath.hh.
References ArmISA::e, ArmISA::n, warn, and X86ISA::x.
Referenced by DRAMCtrl::Rank::flushCmdList(), Pl390::getCpuTarget(), PowerModel::getDynamicPower(), ThermalDomain::getEquation(), PowerModel::getStaticPower(), A9SCU::read(), Sp804::Timer::read(), CpuLocalTimer::Timer::read(), Sp804::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), and DRAMCtrl::Rank::updatePowerStats().
int prevPrime | ( | int | n | ) |
Definition at line 35 of file intmath.cc.
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Definition at line 213 of file intmath.hh.
References ArmISA::mask.
Referenced by AlphaProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), RiscvProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), brkFunc(), TLBCoalescer::canCoalesce(), Shader::doFunctionalAccess(), Process::fixupStackFault(), X86ISA::GpuTLB::handleFuncTranslationReturn(), StackDistProbe::handleRequest(), FetchUnit::initiateFetch(), TimingSimpleCPU::initiateMemRead(), X86ISA::GpuTLB::issueTLBLookup(), BasePrefetcher::pageAddress(), TLBCoalescer::IssueProbeEvent::process(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), TLBCoalescer::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), BasePrefetcher::samePage(), BaseDynInst< Impl >::splitRequest(), SETranslatingPortProxy::tryMemsetBlob(), SETranslatingPortProxy::tryWriteBlob(), ComputeUnit::updatePageDivergenceDist(), TLBCoalescer::updatePhysAddresses(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), and CheckerCPU::writeMem().
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Definition at line 205 of file intmath.hh.
References ArmISA::mask.
Referenced by StorageSpace::addSymbol(), AlphaProcess::AlphaProcess(), AlphaProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), RiscvProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), ArmProcess32::ArmProcess32(), ArmProcess64::ArmProcess64(), brkFunc(), ChunkGenerator::ChunkGenerator(), HsailCode::generateHsaKernelInfo(), X86ISA::I386Process::I386Process(), X86System::initState(), MipsProcess::MipsProcess(), Shader::mmap(), mmapImpl(), mremapFunc(), PowerProcess::PowerProcess(), RiscvProcess::RiscvProcess(), Sparc32Process::Sparc32Process(), Sparc64Process::Sparc64Process(), Process::updateBias(), and X86ISA::X86_64Process::X86_64Process().