gem5
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#include "pybind11/pybind11.h"
#include <string>
#include "config/the_isa.hh"
#include "mem/mem_object.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "sim/full_system.hh"
Go to the source code of this file.
Functions | |
static int | connectPorts (SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2) |
Connect the described MemObject ports. More... | |
void | pybind_init_pyobject (py::module &m_native) |
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static |
Connect the described MemObject ports.
Called from Python. The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. SimObject1 is the master, and SimObject2 is the slave
Definition at line 88 of file pyobject.cc.
References BaseMasterPort::bind(), MemObject::getMasterPort(), MemObject::getSlavePort(), SimObject::name(), panic, and EtherInt::setPeer().
Referenced by pybind_init_pyobject().
void pybind_init_pyobject | ( | py::module & | m_native | ) |
Definition at line 147 of file pyobject.cc.
References connectPorts(), and ArmISA::m.