simple_mem.hh

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/*
 * Copyright (c) 2012-2013 ARM Limited
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * Authors: Ron Dreslinski
 *          Andreas Hansson
 */

#ifndef __SIMPLE_MEMORY_HH__
#define __SIMPLE_MEMORY_HH__

#include <list>

#include "mem/abstract_mem.hh"
#include "mem/port.hh"
#include "params/SimpleMemory.hh"

class SimpleMemory : public AbstractMemory
{

  private:

    class DeferredPacket
    {

      public:

        const Tick tick;
        const PacketPtr pkt;

        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
    };

    class MemoryPort : public SlavePort
    {

      private:

        SimpleMemory& memory;

      public:

        MemoryPort(const std::string& _name, SimpleMemory& _memory);

      protected:

        Tick recvAtomic(PacketPtr pkt);

        void recvFunctional(PacketPtr pkt);

        bool recvTimingReq(PacketPtr pkt);

        void recvRespRetry();

        AddrRangeList getAddrRanges() const;

    };

    MemoryPort port;

    const Tick latency;

    const Tick latency_var;

    std::list<DeferredPacket> packetQueue;

    const double bandwidth;

    bool isBusy;

    bool retryReq;

    bool retryResp;

    void release();

    EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;

    void dequeue();

    EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;

    Tick getLatency() const;

    std::unique_ptr<Packet> pendingDelete;

  public:

    SimpleMemory(const SimpleMemoryParams *p);

    DrainState drain() override;

    BaseSlavePort& getSlavePort(const std::string& if_name,
                                PortID idx = InvalidPortID) override;
    void init() override;

  protected:

    Tick recvAtomic(PacketPtr pkt);

    void recvFunctional(PacketPtr pkt);

    bool recvTimingReq(PacketPtr pkt);

    void recvRespRetry();

};

#endif //__SIMPLE_MEMORY_HH__