- b -
- b
: m5_twin32_t
, m5_twin64_t
- ba
: PowerISA::CondLogicOp
- backendLatency
: DRAMCtrl
- backingStore
: PhysicalMemory
- badvaddr
: MipsISA::RemoteGDB::MipsGdbRegCache
- bandwidth
: SimpleMemory
- bank
: DRAMCtrl::Bank
, DRAMCtrl::Command
, DRAMCtrl::DRAMPacket
- bankBits
: BankedArray
, DramGen
- bankConflictPenalty
: LdsState
- bankedRegs
: Pl390
- bankgr
: DRAMCtrl::Bank
- bankGroupArch
: DRAMCtrl
- bankGroupsPerRank
: DRAMCtrl
- bankId
: DRAMCtrl::DRAMPacket
- bankRef
: DRAMCtrl::DRAMPacket
- banks
: BankedArray
, DRAMCtrl::Rank
, LdsState
- banksPerRank
: DRAMCtrl
- bankType
: MipsISA::ISA
- BAR0_SIZE_BASE
: PciVirtIO
- BARAddrs
: PciDevice
- barCnt
: Wavefront
- barrier
: BaseGlobalEvent
- barrier_id
: ComputeUnit
- barrierCnt
: Wavefront
- barrierEvent
: BaseGlobalEvent
- barrierId
: Wavefront
- barrierSlots
: Wavefront
- BARSize
: PciDevice
- base
: ArmFreebsdProcessBits::SyscallTable
, ArmISA::Memory64
, ArmISA::Memory
, ArmISA::RfeOp
, ArmISA::Swap
, ArmISA::SysDC64
, ArmLinuxProcessBits::SyscallTable
, Brig::BrigDirectiveArgBlockEnd
, Brig::BrigDirectiveArgBlockStart
, Brig::BrigDirectiveComment
, Brig::BrigDirectiveControl
, Brig::BrigDirectiveExecutable
, Brig::BrigDirectiveExtension
, Brig::BrigDirectiveFbarrier
, Brig::BrigDirectiveLabel
, Brig::BrigDirectiveLoc
, Brig::BrigDirectiveModule
, Brig::BrigDirectiveNone
, Brig::BrigDirectivePragma
, Brig::BrigDirectiveVariable
, Brig::BrigInstAddr
, Brig::BrigInstAtomic
, Brig::BrigInstBase
, Brig::BrigInstBasic
, Brig::BrigInstBr
, Brig::BrigInstCmp
, Brig::BrigInstCvt
, Brig::BrigInstImage
, Brig::BrigInstLane
, Brig::BrigInstMem
, Brig::BrigInstMemFence
, Brig::BrigInstMod
, Brig::BrigInstQueryImage
, Brig::BrigInstQuerySampler
, Brig::BrigInstQueue
, Brig::BrigInstSeg
, Brig::BrigInstSegCvt
, Brig::BrigInstSignal
, Brig::BrigInstSourceType
, Brig::BrigOperandAddress
, Brig::BrigOperandAlign
, Brig::BrigOperandCodeList
, Brig::BrigOperandCodeRef
, Brig::BrigOperandConstantBytes
, Brig::BrigOperandConstantImage
, Brig::BrigOperandConstantOperandList
, Brig::BrigOperandConstantSampler
, Brig::BrigOperandOperandList
, Brig::BrigOperandRegister
, Brig::BrigOperandString
, Brig::BrigOperandWavesize
, cp::Format
, EmbeddedPyBind
, TimeBuffer< T >
, X86ISA::EmulEnv
, X86ISA::I386Process::VSyscallPage
, X86ISA::MemOp
, X86ISA::X86_64Process::VSyscallPage
- base_addr
: UserDesc64
- baseAddr
: ObjectFile::Section
, PCIConfig
- baseaddr
: Pl111
- baseAddr
: PrdEntry
, UFSHostDevice::UFSHCDSGEntry
- baseAddr1
: MemTest
- baseAddr2
: MemTest
- baseCCRegIndex
: PhysRegFile
- baseCpu
: ThreadState
- baseEntries
: X86ISA::IntelMP::ConfigTable
- baseFilename
: CheckpointIn
- baseFloatRegIndex
: PhysRegFile
- baseIsSP
: ArmISA::Memory64
- basename
: MathExprPowerModel
- basePC
: X86ISA::Decoder
- basePtr
: MultiLevelPageTable< ISAOps >
, Wavefront
- basicBlocks
: ControlFlowInfo
- bb
: PowerISA::CondLogicOp
- bbMap
: SimPoint
- bc
: GPUDynInst
- bcd
: Intel8254Timer
, Pl111
- bCond
: Barrier
- bdelayDoneSeqNum
: DefaultDecode< Impl >
- bebo
: Pl111
- bepo
: Pl111
- bf
: PowerISA::CondMoveOp
- bfa
: PowerISA::CondMoveOp
- bgr
: Pl111
- bi
: PowerISA::BranchCond
- big_endian
: HDLcd
- bigendian
: VncInput::PixelFormat
- bigPkt
: TimingSimpleCPU::SplitFragmentSenderState
- bigThumb
: ArmISA::Decoder
- bimodalIndex
: LTAGE::BranchInfo
- binary
: MathExpr::OpSearch
- bindToLoopback
: ListenSocket
- bist
: PCIConfig
- BitCount
: Bitmap::InfoHeaderV1
- bits
: ImmOperand< T >
, MSIXPbaEntry
, Set
- blank_space
: cp::Format
- bldrev
: aout_exechdr
- blk
: CacheBlkPrintWrapper
- blkAddr
: QueueEntry
- blkMask
: BaseTags
- blks
: BaseSetAssoc
, CacheSet< Blktype >
, FALRU
- blkSize
: BaseCache
, BasePrefetcher
, BaseTags
, QueueEntry
, UFSHostDevice::UFSSCSIDevice
- block
: FlashDevice::PageMapEntry
- blockAddrMask
: MemTest
- blockBits
: DramGen
- blocked
: BaseCache
, BaseCache::CacheSlavePort
, Minor::Decode::DecodeThreadInfo
, Minor::Fetch1::Fetch1ThreadInfo
, Minor::Fetch2::Fetch2ThreadInfo
- blocked_causes
: BaseCache
- blocked_cycles
: BaseCache
- blockedCycle
: BaseCache
- blockedMemInsts
: InstructionQueue< Impl >
- blockEmptyEntries
: FlashDevice
- blockSize
: FlashDevice
- blocksize
: LinearGen
- blockSize
: MemTest
- blocksize
: RandomGen
, TraceCPU::FixedRetryGen::TraceElement
, TraceGen::TraceElement
- blockSizeBits
: GarnetSyntheticTraffic
- blocksPerDisk
: FlashDevice
- blockThisCycle
: DefaultRename< Impl >
- blockValidEntries
: FlashDevice
- blue
: Bitmap::BmpPixel32
, Pixel
- blue_select
: HDLcd
- bluemax
: VncInput::PixelFormat
- blueshift
: VncInput::PixelFormat
- bmEnabled
: IdeController
- bmiAddr
: IdeController
- bmiSize
: IdeController
- bmp
: HDLcd
, Pl111
- bMutex
: Barrier
- bo
: PowerISA::BranchCond
- bootldr
: ArmSystem
- bootLoaders
: ArmSystem
- bootReleaseAddr
: FreebsdArmSystem
- bottomDW
: X86ISA::I82094AA
- bottomReserved
: X86ISA::I82094AA
- box_tick_cnt
: Shader
- bpHistory
: BPredUnit::PredictorHistory
- bpp
: VncInput::PixelFormat
- branchAddr
: TimeBufStruct< Impl >::decodeComm
- branchCount
: TimeBufStruct< Impl >::decodeComm
- branchInp
: Minor::Fetch2
- branchMispredict
: DefaultIEWDefaultCommit< Impl >
, TimeBufStruct< Impl >::decodeComm
- branchMispredicts
: DefaultCommit< Impl >
, DefaultIEW< Impl >
- branchPC
: LTAGE::BranchInfo
- branchPred
: BaseSimpleCPU
, DefaultFetch< Impl >
- branchPredictor
: Minor::Fetch2
- branchRate
: DefaultFetch< Impl >
- branchTaken
: DefaultIEWDefaultCommit< Impl >
, TimeBufStruct< Impl >::commitComm
, TimeBufStruct< Impl >::decodeComm
- brar
: dp_regs
- brdr
: dp_regs
- bridge
: Bridge::BridgeMasterPort
, Bridge::BridgeSlavePort
- brigInstBase
: HsailISA::MachInst
- brigMajor
: Brig::BrigModuleHeader
- brigMinor
: Brig::BrigModuleHeader
- brigObj
: HsailISA::MachInst
- brigSymbol
: StorageElement
- bsize
: aout_exechdr
, ecoff_aouthdr
- bss
: ObjectFile
- bss_start
: aout_exechdr
, ecoff_aouthdr
- bt
: PowerISA::CondLogicOp
, TIR
- btable
: LTAGE
- BTB
: BPredUnit
- btb
: DefaultBTB
- BTBCorrect
: BPredUnit
- BTBHitPct
: BPredUnit
- BTBHits
: BPredUnit
- BTBLookups
: BPredUnit
- bubbleFlag
: Minor::ForwardLineData
- bubbleInst
: Minor::MinorDynInst
- bucket_size
: Stats::DistData
, Stats::DistStor
, Stats::DistStor::Params
, Stats::HistStor
- buckets
: Stats::DistStor::Params
, Stats::HistStor::Params
- buf
: CircleBuf< T >
, Fifo< T >
, iGbReg::RxDesc
- buff_per_vc
: FaultModel::system_conf
- buffer
: DmaReadFifo
, EtherTapBase
, Minor::Latch< Data >
, TimeBuffer< T >::wire
, UFSHostDevice::transferInfo
, VPtr< T >
- buffer_size
: Pl111
- buffer_used
: EtherTapStub
- bufferram
: AlphaLinux::tgt_sysinfo
, ArmLinux32::tgt_sysinfo
, ArmLinux64::tgt_sysinfo
, MipsLinux::tgt_sysinfo
, Sparc32Linux::tgt_sysinfo
, SparcLinux::tgt_sysinfo
, X86Linux32::tgt_sysinfo
, X86Linux64::tgt_sysinfo
- buflen
: EtherTapBase
- bufLength
: EthPacketData
- bufPtr
: BaseBufferArg
- bufptr
: ns_desc32
, ns_desc64
- burst_len
: HDLcd
- burstCount
: DRAMCtrl::BurstHelper
- burstHelper
: DRAMCtrl::DRAMPacket
- burstLength
: DRAMCtrl
- burstSize
: DRAMCtrl
- burstsServiced
: DRAMCtrl::BurstHelper
- bus
: EtherBus::DoneEvent
, PciBusAddr
- bus_options
: HDLcd
- BUS_OPTIONS_RESETV
: HDLcd
- busAddr
: PciHost::DeviceInterface
- busBusyUntil
: DRAMCtrl
- busID
: X86ISA::IntelMP::AddrSpaceMapping
, X86ISA::IntelMP::Bus
, X86ISA::IntelMP::BusHierarchy
, X86ISA::IntelMP::CompatAddrSpaceMod
- busState
: DRAMCtrl
- busStateNext
: DRAMCtrl
- busType
: X86ISA::IntelMP::Bus
- busUtil
: DRAMCtrl
- busUtilRead
: DRAMCtrl
- busUtilWrite
: DRAMCtrl
- busy
: ConditionRegisterState
, CopyEngine::CopyEngineChannel
, Iob::IntBusy
, VectorRegisterFile
- busyBanks
: BankedArray
- button_mask
: VncInput::PointerEventMessage
- bwInstRead
: AbstractMemory
- bwRead
: AbstractMemory
- bwTotal
: AbstractMemory
- bwWrite
: AbstractMemory
- byte_order
: PixelConverter
- byte_trackers
: MemChecker
- byteCount
: Brig::BrigBase
, Brig::BrigData
, Brig::BrigModuleHeader
, Brig::BrigSectionHeader
, PrdEntry
- byteMask
: MsrBase
- bytes
: Brig::BrigData
, Brig::BrigOperandConstantBytes
- bytes_completed
: DMARequest
- bytes_issued
: DMARequest
- bytes_per_pixel
: HDLcd
- bytesAccessed
: DRAMCtrl::Bank
- bytesAllocated
: LdsState
- bytesCopied
: CopyEngine
, IGbE::RxDescCache
- bytesInstRead
: AbstractMemory
- bytesPerActivate
: DRAMCtrl
- bytesPerPixel
: Pl111
- bytesRead
: AbstractMemory
- bytesReadDRAM
: DRAMCtrl
- bytesReadSys
: DRAMCtrl
- bytesReadWrQ
: DRAMCtrl
- bytesValid
: Packet
- bytesWritten
: AbstractMemory
, DRAMCtrl
- bytesWrittenSys
: DRAMCtrl
Generated on Fri Jun 9 2017 13:04:45 for gem5 by doxygen 1.8.6