- c -
- c
: ArmISA::PMU
, AtomicOpCAS< T >
, Cycles
, MathExpr::OpSearch
- C0
: MipsISA::PTE
, PowerISA::PTE
, RiscvISA::PTE
- c0_config
: SparcISA::TLB
- c0_tsb_ps0
: SparcISA::TLB
- c0_tsb_ps1
: SparcISA::TLB
- C1
: MipsISA::PTE
, PowerISA::PTE
, RiscvISA::PTE
- c_reg
: ConditionRegisterState
- cache
: BasePrefetcher
, BaseTags
, Cache::CacheReqPacketQueue
, Cache::CpuSidePort
, Cache::MemSidePort
, CacheBlkVisitorWrapper
- cacheAsi
: SparcISA::TLB
- cacheBlkSize
: DefaultFetch< Impl >
- cacheBlocked
: DefaultFetch< Impl >
, LSQUnit< Impl >::LSQSenderState
- cacheBlockMask
: AtomicSimpleCPU::AtomicCPUDPort
, LSQUnit< Impl >
, Minor::LSQ
, TimingSimpleCPU::DcachePort
- cacheBoundaries
: FALRU
- cachedDisassembly
: StaticInst
- cachedLocations
: SnoopFilter
- cachedMsrIntersection
: X86KvmCPU
- cachedPC
: PowerISA::PCDependentDisassembly
- cachedSymtab
: PowerISA::PCDependentDisassembly
- cacheEntry
: SparcISA::TLB
- cacheLines
: MemFootprintProbe
- cacheLinesAll
: MemFootprintProbe
- cacheLineSize
: PCIConfig
- cacheLineSizeLg2
: MemFootprintProbe
- cacheMask
: FALRU
- cachePnt
: IGbE::DescCache< T >
- cachePort
: GarnetSyntheticTraffic
- cacheSnoop
: QueuedPrefetcher
- cacheState
: SparcISA::TLB
- cacheStorePorts
: LSQUnit< Impl >
- cacheValid
: SparcISA::TLB
- cachingPage
: UFSHostDevice::UFSSCSIDevice
- calc
: StackDistProbe
- callArgMem
: Wavefront
- callArgs
: ListOperand
- callback
: DmaCallback::DmaChunkEvent
- callbackDataAvail
: Uart
, VirtIOConsole
- callbackKick
: PciVirtIO
- callbacks
: CallbackQueue
- canEarlyIssue
: Minor::MinorDynInst
- canHandleInterrupts
: DefaultCommit< Impl >
- cantForwardFromFUIndices
: Minor::FUPipeline
, MinorFU
- canWB
: LSQUnit< Impl >::SQEntry
- capabilityList
: FuncUnit
, FUPool
, Minor::FUPipeline
, MinorOpClassSet
- capabilityPtr
: PCIConfig
- capacitors
: ThermalModel
- capacity
: Minor::Queue< ElemType, ReportTraits, BubbleTraits >
, VirtIOBlock::Config
- capacityLower
: UFSHostDevice::UFSSCSIDevice
- capacityUpper
: UFSHostDevice::UFSSCSIDevice
- caplen
: pcap_pkthdr
- captureBitmap
: VncInput
- captureCurrentFrame
: VncInput
- captureEnabled
: VncInput
- captureLastHash
: VncInput
- captureOutputDirectory
: VncInput
- cardbusCIS
: PCIConfig
- cascadeBits
: X86ISA::I8259
- cascadeMode
: X86ISA::I8259
- cause
: CountedExitEvent
, GlobalSimLoopExitEvent
, LocalSimLoopExitEvent
, MipsISA::RemoteGDB::MipsGdbRegCache
- caux
: ecoff_fdr
- cbAuxOffset
: ecoff_symhdr
- cbDnOffset
: ecoff_symhdr
- cbExtOffset
: ecoff_symhdr
- cbFdOffset
: ecoff_symhdr
- cbLine
: ecoff_fdr
, ecoff_symhdr
- cbLineOffset
: ecoff_fdr
, ecoff_symhdr
, pdr
- cbOptOffset
: ecoff_symhdr
- cbPdOffset
: ecoff_symhdr
- cbRfdOffset
: ecoff_symhdr
- cbSs
: ecoff_fdr
- cbSsExtOffset
: ecoff_symhdr
- cbSsOffset
: ecoff_symhdr
- cbSymOffset
: ecoff_symhdr
- cchip
: Malta
, Tsunami
- ccList
: UnifiedFreeList
- ccMap
: UnifiedRenameMap
- ccreg
: ArmISA::AnyReg
- ccReg
: X86ISA::AnyReg
- ccRegFile
: PhysRegFile
- ccRegfileReads
: FullO3CPU< Impl >
- ccRegfileWrites
: FullO3CPU< Impl >
- ccsr
: dp_regs
- cdf
: Stats::ScalarPrint
- ce
: CopyEngine::CopyEngineChannel
- cePort
: CopyEngine::CopyEngineChannel
- ch_b
: PixelConverter
- ch_g
: PixelConverter
- ch_r
: PixelConverter
- chan
: CopyEngine
- chanCount
: CopyEngineReg::Regs
- changed
: Trace::ArmNativeTrace::ThreadState
- changedPC
: CheckerCPU
- changedROBNumEntries
: DefaultCommit< Impl >
- channelId
: CopyEngine::CopyEngineChannel
- channelOrder
: Brig::BrigOperandConstantImage
- channels
: DRAMCtrl
- channelType
: Brig::BrigOperandConstantImage
- characteristicExtBytes
: X86ISA::SMBios::BiosInformation
- characteristics
: X86ISA::SMBios::BiosInformation
- checkEmptyROB
: DefaultCommit< Impl >
- checker
: BaseSimpleCPU
, FullO3CPU< Impl >
- checkerCPU
: CheckerThreadContext< TC >
- checkerTC
: CheckerThreadContext< TC >
- checkLoads
: LSQUnit< Impl >
- checkR11
: Trace::X86NativeTrace
- checkRcx
: Trace::X86NativeTrace
- checkStartEvent
: RubyTester
- child
: CowDiskImage
- childClearTID
: Process
- children
: ClockDomain
, ProfileNode
- choiceCounters
: BiModeBP
- choiceCtrBits
: BiModeBP
, TournamentBP
- choiceCtrs
: TournamentBP
- choiceHistoryMask
: BiModeBP
, TournamentBP
- choicePredictorSize
: BiModeBP
, TournamentBP
- choiceThreshold
: BiModeBP
, TournamentBP
- chunk
: LdsChunk
- chunkIdx
: X86ISA::Decoder
- chunkMap
: LdsState
- chunks
: X86ISA::Decoder::InstBytes
- chunkSize
: ChunkGenerator
- ci
: LTAGE::BranchInfo
- ckptCount
: Serializable
- ckptMaxCount
: Serializable
- ckptPrevCount
: Serializable
- ckptRestore
: DistIface::RecvScheduler
- classCode
: PCIConfig
- ClcdCrsrClip
: Pl111
- clcdCrsrClip
: Pl111
- ClcdCrsrConfig
: Pl111
- clcdCrsrConfig
: Pl111
- ClcdCrsrCtrl
: Pl111
- clcdCrsrCtrl
: Pl111
- ClcdCrsrIcr
: Pl111
- clcdCrsrIcr
: Pl111
- ClcdCrsrImsc
: Pl111
- clcdCrsrImsc
: Pl111
- ClcdCrsrMis
: Pl111
- clcdCrsrMis
: Pl111
- ClcdCrsrPalette0
: Pl111
- clcdCrsrPalette0
: Pl111
- ClcdCrsrPalette1
: Pl111
- clcdCrsrPalette1
: Pl111
- ClcdCrsrRis
: Pl111
- clcdCrsrRis
: Pl111
- ClcdCrsrXY
: Pl111
- clcdCrsrXY
: Pl111
- cleanupEvent
: TLBCoalescer
, X86ISA::GpuTLB
- cleanupQueue
: TLBCoalescer
, X86ISA::GpuTLB
- clearFetchFault
: DefaultFetchDefaultDecode< Impl >
- clearInterrupt
: TimeBufStruct< Impl >::commitComm
- clearPeriod
: StoreSet
- cline
: ecoff_fdr
- clk_in
: Pl050
- clkdiv
: Pl050
- clksel
: Pl111
- clock
: Shader
, Sp804::Timer
, TLBCoalescer
, X86ISA::GpuTLB
- clock_data
: MC146818
- clock_remainder
: ArmISA::PMU
- clockDivider
: DerivedClockDomain
- clockDomain
: Clocked
- clocked_object
: PowerModel
, PowerModelState
- clockID
: PosixKvmTimer
- ClrImportant
: Bitmap::InfoHeaderV1
- ClrUsed
: Bitmap::InfoHeaderV1
- clusivity
: Cache
- cmap
: Stats::SparseHistData
, Stats::SparseHistStor
- cmd
: GdbCommand::Context
, MemCmd
, Packet
, ProbePoints::PacketInfo
, TraceCPU::FixedRetryGen::TraceElement
, TraceGen::TraceElement
- cmd_byte
: GdbCommand::Context
- cmdBytes
: IdeDisk
- cmdBytesLeft
: IdeDisk
- cmdList
: DRAMCtrl::Rank
- cmdReg
: IdeDisk
- cmdsts
: ns_desc32
, ns_desc64
- CMDUCMDARG1
: UFSHostDevice::HCIMem
- CMDUCMDARG2
: UFSHostDevice::HCIMem
- CMDUCMDARG3
: UFSHostDevice::HCIMem
- CMDUICCMDR
: UFSHostDevice::HCIMem
- cmos
: SouthBridge
- cmpOp
: HsailISA::CmpInstBase< DestOperandType, SrcOperandType >
- co
: ClockedObjectDumpCallback
- coalescedAccesses
: TLBCoalescer
- coalescedRxDesc
: EtherDevice
- coalescedRxIdle
: EtherDevice
- coalescedRxOk
: EtherDevice
- coalescedRxOrn
: EtherDevice
- coalescedSwi
: EtherDevice
- coalescedTotal
: EtherDevice
- coalescedTxDesc
: EtherDevice
- coalescedTxIdle
: EtherDevice
- coalescedTxOk
: EtherDevice
- coalescer
: TLBCoalescer::CleanupEvent
, TLBCoalescer::CpuSidePort
, TLBCoalescer::IssueProbeEvent
, TLBCoalescer::MemSidePort
- coalescerFIFO
: TLBCoalescer
- coalescerToVrfBusWidth
: ComputeUnit
- coalescingWindow
: TLBCoalescer
- cobol_main
: ecoff_extsym
- code
: EmbeddedPython
, GlobalSimLoopExitEvent
, LocalSimLoopExitEvent
, MipsISA::MipsFaultBase::FaultVals
- code_offs
: HsaKernelInfo
- code_ptr
: HsaQueueEntry
- code_size
: HsaDriverSizes
- codeFiles
: ClDriver
- coissue_return
: Shader
- colAllowedAt
: DRAMCtrl::Bank
- cols
: VirtIOConsole::Config
- column
: Brig::BrigDirectiveLoc
- columnsPerRowBuffer
: DRAMCtrl
- columnsPerStripe
: DRAMCtrl
- command
: CommandReg
, CopyEngineReg::ChanRegs
, CopyEngineReg::DmaDesc
, dp_regs
, HDLcd
, PCIConfig
- Command
: Sinic::Device
- command_map
: BaseRemoteGDB
- commandByte
: X86ISA::I8042
- commandDescBaseAddrHi
: UFSHostDevice::UTPTransferReqDesc
- commandDescBaseAddrLo
: UFSHostDevice::UTPTransferReqDesc
- commandInfo
: MemCmd
- commandLast
: X86ISA::I8042
- commandLine
: LinuxX86System
- CommandLineSize
: BareIronMipsSystem
, LinuxAlphaSystem
, LinuxMipsSystem
- commandPort
: X86ISA::I8042
- commandUPIU
: UFSHostDevice::UTPTransferCMDDesc
- commit
: DefaultCommit< Impl >::TrapEvent
, DefaultRename< Impl >::Stalls
, ElasticTrace::TraceInfo
, FullO3CPU< Impl >
- commit_ptr
: DefaultRename< Impl >
- commitEligibleSamples
: DefaultCommit< Impl >
- commitInfo
: TimeBufStruct< Impl >
- commitLimit
: Minor::Execute
- commitNonSpecStalls
: DefaultCommit< Impl >
- commitPolicy
: DefaultCommit< Impl >
- commitPriority
: Minor::Execute
- commitRenameMap
: FullO3CPU< Impl >
- commitSquashedInsts
: DefaultCommit< Impl >
- commitStatus
: DefaultCommit< Impl >
- committed
: LSQUnit< Impl >::SQEntry
- committedInsts
: FullO3CPU< Impl >
- committedInstType
: Minor::MinorStats
- committedOps
: FullO3CPU< Impl >
- committedStores
: DefaultCommit< Impl >
- commitTick
: ElasticTrace::TraceInfo
- commitToDecodeDelay
: DefaultDecode< Impl >
- commitToFetchDelay
: DefaultFetch< Impl >
- commitToIEWDelay
: DefaultCommit< Impl >
, DefaultIEW< Impl >
, InstructionQueue< Impl >
- commitToRenameDelay
: DefaultRename< Impl >
- commitWidth
: DefaultCommit< Impl >
, DefaultRename< Impl >
- commPage
: ArmFreebsdProcess32
, ArmLinuxProcess32
- comp
: LTAGE::FoldedHistory
- compare
: Brig::BrigInstCmp
- compDelay
: ElasticTrace::TraceInfo
, TraceCPU::ElasticDataGen::GraphNode
- compLength
: LTAGE::FoldedHistory
- complete
: ArmISA::Stage2LookUp
, MemChecker::Transaction
, MemChecker::WriteCluster
- COMPLETED
: ArmISA::TableWalker
- completed
: LSQUnit< Impl >::SQEntry
, MemDepUnit< MemDepPred, Impl >::MemDepEntry
- completedWfs
: ComputeUnit
- completeMax
: MemChecker::WriteCluster
- completionAddr
: CopyEngineReg::ChanRegs
- completionAddress
: IGbE::TxDescCache
- completionDataReg
: CopyEngine::CopyEngineChannel
- completionEnabled
: IGbE::TxDescCache
- completionEvent
: DmaPort::DmaReqState
- Compression
: Bitmap::InfoHeaderV1
- computeIndices
: LTAGE::ThreadHistory
- computeTags
: LTAGE::ThreadHistory
- computeUnit
: AtomicOpCAS< T >
, ComputeUnit::CUExitCallback
, ComputeUnit::DataPort
, ComputeUnit::DTLBPort
, ComputeUnit::ITLBPort
, ComputeUnit::LDSPort
, ComputeUnit::SQCPort
, ConditionRegisterState
, ExecStage
, FetchStage
, FetchUnit
, GlobalMemPipeline
, LocalMemPipeline
, ScheduleStage
, ScoreboardCheckStage
, VecRegisterState
, VectorRegisterFile
, Wavefront
- cond
: ArmISA::FpRegRegRegCondOp
, HsailISA::CbrInstBase< TargetType >
, TimingExprIf
- condBranch
: LTAGE::BranchInfo
- condCode
: ArmISA::BranchImmCond64
, ArmISA::DataXCondCompImmOp
, ArmISA::DataXCondCompRegOp
, ArmISA::DataXCondSelOp
, ArmISA::FpCondCompRegOp
, ArmISA::FpCondSelOp
, ArmISA::PredOp
- condIncorrect
: BPredUnit
- condPredicted
: BPredUnit
- condRegState
: Wavefront
- confBase
: GenericPciHost
- confDeviceBits
: GenericPciHost
- confidence
: LTAGE::LoopEntry
, StridePrefetcher::StrideEntry
- config
: dp_regs
, PciDevice
- Config
: Sinic::Device
- config
: VirtIO9PBase
, VirtIOBlock
, VirtIOConsole
- configAddress
: X86ISA::GpuTLB
, X86ISA::TLB
- configDelay
: PciDevice
- configFile
: CxxConfigManager
, TrafficGen
- configManager
: CxxConfigManager::SimObjectResolver
- configSize
: VirtIODeviceBase
- configurations
: FaultModel
- conflictingLoads
: MemDepUnit< MemDepPred, Impl >
- conflictingStores
: MemDepUnit< MemDepPred, Impl >
- confSize
: GenericPciHost
- confTableReported
: AbstractMemory
, BackingStoreEntry
- console
: AlphaSystem
, MipsISA::StackTrace
, MipsSystem
, PowerISA::StackTrace
, RiscvISA::StackTrace
, RiscvSystem
, X86ISA::StackTrace
- consoleData
: AlphaBackdoor
- consolePanicEvent
: AlphaSystem
, MipsSystem
, RiscvSystem
- consoleSymtab
: AlphaSystem
, MipsSystem
, RiscvSystem
- constUDelaySkipEvent
: FreebsdArmSystem
, LinuxArmSystem
- consumerInst
: DefaultIEW< Impl >
- cont
: cp::Print
- context
: BaseRemoteGDB
- contextId
: CacheBlk::Lock
, LockedAddr
, SparcISA::TlbRange
- contextIds
: Process
- continued
: TIR
- control
: Brig::BrigDirectiveControl
, Pl011
, Sp804::Timer
- controlFlowDivergenceDist
: ComputeUnit
- controller
: AbstractController::MemoryPort
- controlPage
: UFSHostDevice::UFSSCSIDevice
- conv
: HDLcd
- converter
: Pl111
- coord
: Brig::BrigOperandConstantSampler
- coordType
: Brig::BrigInstImage
- copiesProcessed
: CopyEngine
- coProcID
: MipsISA::CoprocessorUnusableFault
- copt
: ecoff_fdr
- copyBuffer
: CopyEngine::CopyEngineChannel
- count
: ArmISA::ArmFault::FaultVals
, AUXU
, DmaCallback
, InstructionQueue< Impl >
, ProfileNode
, RefCounted
, SimPoint::BBInfo
, SparcISA::SparcFaultBase::FaultVals
- counter
: Intel8254Timer
, Intel8254Timer::Counter::CounterEvent
, SatCounter
- counters
: ArmISA::PMU
- countInt
: UFSHostDevice
- countNumSeqPkts
: DramGen
- countPages
: ComputeUnit
- cp0
: MipsISA::ISA::CP0Event
- CP0_Config
: MipsISA::CoreSpecific
- CP0_Config1
: MipsISA::CoreSpecific
- CP0_Config1_C2
: MipsISA::CoreSpecific
- CP0_Config1_CA
: MipsISA::CoreSpecific
- CP0_Config1_DA
: MipsISA::CoreSpecific
- CP0_Config1_DL
: MipsISA::CoreSpecific
- CP0_Config1_DS
: MipsISA::CoreSpecific
- CP0_Config1_EP
: MipsISA::CoreSpecific
- CP0_Config1_FP
: MipsISA::CoreSpecific
- CP0_Config1_IA
: MipsISA::CoreSpecific
- CP0_Config1_IL
: MipsISA::CoreSpecific
- CP0_Config1_IS
: MipsISA::CoreSpecific
- CP0_Config1_M
: MipsISA::CoreSpecific
- CP0_Config1_MD
: MipsISA::CoreSpecific
- CP0_Config1_MMU
: MipsISA::CoreSpecific
- CP0_Config1_PC
: MipsISA::CoreSpecific
- CP0_Config1_WR
: MipsISA::CoreSpecific
- CP0_Config2
: MipsISA::CoreSpecific
- CP0_Config2_M
: MipsISA::CoreSpecific
- CP0_Config2_SA
: MipsISA::CoreSpecific
- CP0_Config2_SL
: MipsISA::CoreSpecific
- CP0_Config2_SS
: MipsISA::CoreSpecific
- CP0_Config2_SU
: MipsISA::CoreSpecific
- CP0_Config2_TA
: MipsISA::CoreSpecific
- CP0_Config2_TL
: MipsISA::CoreSpecific
- CP0_Config2_TS
: MipsISA::CoreSpecific
- CP0_Config2_TU
: MipsISA::CoreSpecific
- CP0_Config3
: MipsISA::CoreSpecific
- CP0_Config3_DSPP
: MipsISA::CoreSpecific
- CP0_Config3_LPA
: MipsISA::CoreSpecific
- CP0_Config3_M
: MipsISA::CoreSpecific
- CP0_Config3_MT
: MipsISA::CoreSpecific
- CP0_Config3_SM
: MipsISA::CoreSpecific
- CP0_Config3_SP
: MipsISA::CoreSpecific
- CP0_Config3_TL
: MipsISA::CoreSpecific
- CP0_Config3_VEIC
: MipsISA::CoreSpecific
- CP0_Config3_VInt
: MipsISA::CoreSpecific
- CP0_Config_AR
: MipsISA::CoreSpecific
- CP0_Config_AT
: MipsISA::CoreSpecific
- CP0_Config_BE
: MipsISA::CoreSpecific
- CP0_Config_MT
: MipsISA::CoreSpecific
- CP0_Config_VI
: MipsISA::CoreSpecific
- CP0_EBase_CPUNum
: MipsISA::CoreSpecific
- CP0_IntCtl_IPPCI
: MipsISA::CoreSpecific
- CP0_IntCtl_IPTI
: MipsISA::CoreSpecific
- CP0_PerfCtr_M
: MipsISA::CoreSpecific
- CP0_PerfCtr_W
: MipsISA::CoreSpecific
- CP0_PRId
: MipsISA::CoreSpecific
- CP0_PRId_CompanyID
: MipsISA::CoreSpecific
- CP0_PRId_CompanyOptions
: MipsISA::CoreSpecific
- CP0_PRId_ProcessorID
: MipsISA::CoreSpecific
- CP0_PRId_Revision
: MipsISA::CoreSpecific
- CP0_SrsCtl_HSS
: MipsISA::CoreSpecific
- CP0_WatchHi_M
: MipsISA::CoreSpecific
- cp0EventRemoveList
: MipsISA::ISA
- cp0EventType
: MipsISA::ISA::CP0Event
- cp0Updated
: MipsISA::ISA
- CP_LdMiss
: GPUCoalescer
- cp_seq
: Trace::InstRecord
- cp_seq_valid
: Trace::InstRecord
- CP_StMiss
: GPUCoalescer
- CP_TCCLdHits
: GPUCoalescer
- CP_TCCStHits
: GPUCoalescer
- CP_TCPLdHits
: GPUCoalescer
- CP_TCPLdTransfers
: GPUCoalescer
- CP_TCPStHits
: GPUCoalescer
- CP_TCPStTransfers
: GPUCoalescer
- cpa
: AnnotateDumpCallback
, IGbE
- CPBR
: VGic
- cpd
: ecoff_fdr
- cpi
: FullO3CPU< Impl >
, Minor::MinorStats
, TraceCPU
- cpl
: Pl111
- cpsr
: ArmISA::RemoteGDB::AArch32GdbRegCache
, ArmISA::RemoteGDB::AArch64GdbRegCache
, ArmISA::TableWalker::WalkerState
, ArmISA::TLB
- cptDir
: CheckpointIn
- cpu
: AlphaBackdoor
, AlphaISA::Interrupts
, ArmISA::Interrupts
, AtomicSimpleCPU::AtomicCPUDPort
, AtomicSimpleCPU::TickEvent
, BaseDynInst< Impl >
, BaseKvmCPU::KVMCpuPort
, BaseKvmCPU::TickEvent
, DefaultCommit< Impl >
, DefaultDecode< Impl >
, DefaultFetch< Impl >
, DefaultIEW< Impl >
, DefaultRename< Impl >
, ElasticTrace
, FullO3CPU< Impl >::DcachePort
, FullO3CPU< Impl >::TickEvent
, GarnetSyntheticTraffic::TickEvent
, GenericTimerISA
, GpuDispatcher
, InstructionQueue< Impl >
, Iob::IntMan
, LSQ< Impl >
, LSQUnit< Impl >
, Minor::Decode
, Minor::ExecContext
, Minor::Execute
, Minor::Fetch1
, Minor::Fetch2
, Minor::LSQ
, Minor::Pipeline
, MinorCPU::MinorCPUPort
, MipsISA::ISA::CP0Event
, O3ThreadContext< class >
, O3ThreadState< class >
, Pl390::PostIntEvent
, PowerISA::Interrupts
, RiscvISA::Interrupts
, ROB< Impl >
, SimpleExecContext
, SparcISA::Interrupts
, TimingSimpleCPU::FetchTranslation
, TimingSimpleCPU::IprEvent
, TimingSimpleCPU::TimingCPUPort
, TimingSimpleCPU::TimingCPUPort::TickEvent
, VGic::PostVIntEvent
, X86ISA::Interrupts
- cpu_id
: Pl390
- cpu_list
: Pl390
- CPU_MAX
: CpuLocalTimer
, Pl390
- cpu_mondo_head
: SparcISA::ISA
- cpu_mondo_tail
: SparcISA::ISA
- CPU_Switch_Pri
: EventBase
- CPU_Tick_Pri
: EventBase
- cpuBpr
: Pl390
- cpuClock
: AlphaAccess
, MipsAccess
- cpuEnabled
: Pl390
- cpuEventList
: CpuEvent
- cpuFlags
: X86ISA::IntelMP::Processor
- cpuHighestInt
: Pl390
- CpuID
: VGic
- cpuIntrEnable
: Sinic::Base
- cpuNum
: CpuLocalTimer::Timer
- cpuPendingIntr
: NSGigE
, Sinic::Base
- cpuPioDelay
: Pl390
- cpuPointer
: Shader
- cpuPpiActive
: Pl390
- cpuPpiPending
: Pl390
- cpuPriority
: Pl390
- cpuRange
: KvmKernelGicV2
, Pl390
- cpuSgiActive
: Pl390
- cpuSgiActiveExt
: Pl390
- cpuSgiPending
: Pl390
- cpuSgiPendingExt
: Pl390
- cpuSidePort
: BaseCache
, TLBCoalescer
, X86ISA::GpuTLB
- cpuSignature
: X86ISA::IntelMP::Processor
- cpuStack
: AlphaAccess
, MipsAccess
- cpuTarget
: Pl390
- cpuThread
: Shader
- cpuWaitList
: FullO3CPU< Impl >
- cr
: CopyEngine::CopyEngineChannel
, PowerISA::RemoteGDB::PowerGdbRegCache
- CRDD
: NSGigE
- creatorID
: X86ISA::ACPI::SysDescTable
- creatorRevision
: X86ISA::ACPI::SysDescTable
- creditQueue
: InputUnit
- cRegCount
: HsaKernelInfo
, HsaQueueEntry
- crfd
: ecoff_fdr
, ecoff_symhdr
- CrsrImage
: Pl111
- CrsrImageSize
: Pl111
- cs
: X86ISA::RemoteGDB::AMD64GdbRegCache
, X86ISA::RemoteGDB::X86GdbRegCache
- csr
: RiscvISA::RemoteGDB::RiscvGdbRegCache
, SparcISA::RemoteGDB::SPARCGdbRegCache
- csr_base
: RiscvISA::RemoteGDB::RiscvGdbRegCache
- csum
: iGbReg::RxDesc
- csym
: ecoff_fdr
- ct0
: LTAGE::BranchInfo
- ct1
: LTAGE::BranchInfo
- CTDD
: NSGigE
- ctr
: AbstractController::StatsCallback
, LTAGE::TageEntry
, Network::StatsCallback
, PowerISA::RemoteGDB::PowerGdbRegCache
- ctrInsts
: BaseKvmCPU
- ctrl
: CopyEngineReg::ChanRegs
, IdeDisk
, iGbReg::Regs
- ctrl32
: FXSave
- ctrl64
: FXSave
- CTRL_CNTACR_BASE
: GenericTimerMem
- CTRL_CNTFRQ
: GenericTimerMem
- CTRL_CNTNSAR
: GenericTimerMem
- CTRL_CNTTIDR
: GenericTimerMem
- CTRL_CNTVOFF_HI_BASE
: GenericTimerMem
- CTRL_CNTVOFF_LO_BASE
: GenericTimerMem
- ctrl_ext
: iGbReg::Regs
- ctrlOffset
: IdeController
- ctrlRange
: GenericTimerMem
- ctrlreg
: AlphaISA::AnyReg
, ArmISA::AnyReg
, MipsISA::AnyReg
, PowerISA::AnyReg
, SparcISA::AnyReg
- ctrlReg
: X86ISA::AnyReg
- cu
: GPUExecContext
- cu_id
: ComputeUnit
, GPUDynInst
- cuExitCallback
: ComputeUnit
- cuList
: Shader
- cuPort
: LdsState
- curAddr
: ChunkGenerator
, Pl111
- curCid
: NDRange
- curDmaDesc
: CopyEngine::CopyEngineChannel
- curDoorbell
: UFSHostDevice::UFSHostDeviceStats
- curFetching
: IGbE::DescCache< T >
- curMacroStaticInst
: BaseSimpleCPU
, CheckerCPU
- curMsg
: Trace::InstPBTrace
- curPrd
: IdeDisk
- curPrdAddr
: IdeDisk
- curPrefixPtr
: Packet::PrintReqState
- currBit
: I2CBus
- currElement
: TraceCPU::FixedRetryGen
, TraceGen
- currELHOffset
: ArmISA::ArmFault::FaultVals
- currELTOffset
: ArmISA::ArmFault::FaultVals
- current
: Stats::AvgStor
, Trace::ArmNativeTrace::ThreadState
- currentBBV
: SimPoint
- currentBBVInstCount
: SimPoint
- currentClock
: ClockDomain
- currentCode
: BrigObject
- currentDirectory
: CheckpointIn
- currentIter
: LTAGE::BranchInfo
, LTAGE::LoopEntry
- currentIterSpec
: LTAGE::LoopEntry
- currentReadSSDQueue
: UFSHostDevice::UFSHostDeviceStats
- currentSCSIQueue
: UFSHostDevice::UFSHostDeviceStats
- currentTemp
: ThermalDomain
- currentVoltage
: VoltageDomain
- currentWriteSSDQueue
: UFSHostDevice::UFSHostDeviceStats
- currState
: ArmISA::TableWalker
, TrafficGen
- currStates
: X86ISA::Walker
- curSector
: IdeDisk
, MmDisk
- curSize
: ChunkGenerator
- cursorImage
: Pl111
- curState
: VncServer
- curStaticInst
: BaseSimpleCPU
, CheckerCPU
- curTask
: GpuDispatcher
- curThread
: BaseSimpleCPU
- curTime
: MC146818
- curTranType
: ArmISA::TLB
- cv
: DistIface::Sync
- cvec
: Stats::DistData
, Stats::DistStor
, Stats::FormulaInfoProxy< Stat >
, Stats::HistStor
, Stats::Vector2dInfo
, Stats::VectorInfoProxy< Stat >
- cwd
: Process
- cwp
: SparcISA::ISA
- cx_config
: SparcISA::TLB
- cx_tsb_ps0
: SparcISA::TLB
- cx_tsb_ps1
: SparcISA::TLB
- cycle
: Clocked
- cycleCounter
: ArmISA::PMU
- cyl_high
: CommandReg
- cyl_low
: CommandReg
Generated on Fri Jun 9 2017 13:04:45 for gem5 by doxygen 1.8.6