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gem5
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gem5
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#include "arch/arm/isa_traits.hh"#include "arch/arm/miscregs.hh"#include "arch/arm/types.hh"#include "base/misc.hh"#include "base/trace.hh"#include "base/types.hh"#include "cpu/static_inst.hh"#include "cpu/thread_context.hh"Go to the source code of this file.
Namespaces | |
| ArmISA | |
Functions | |
| PCState | ArmISA::buildRetPC (const PCState &curPC, const PCState &callPC) |
| bool | ArmISA::testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) |
| template<class TC > | |
| void | ArmISA::zeroRegisters (TC *tc) |
| Function to insure ISA semantics about 0 registers. More... | |
| void | ArmISA::startupCPU (ThreadContext *tc, int cpuId) |
| void | ArmISA::copyRegs (ThreadContext *src, ThreadContext *dest) |
| static void | ArmISA::copyMiscRegs (ThreadContext *src, ThreadContext *dest) |
| void | ArmISA::initCPU (ThreadContext *tc, int cpuId) |
| static bool | ArmISA::inUserMode (CPSR cpsr) |
| static bool | ArmISA::inUserMode (ThreadContext *tc) |
| static bool | ArmISA::inPrivilegedMode (CPSR cpsr) |
| static bool | ArmISA::inPrivilegedMode (ThreadContext *tc) |
| bool | ArmISA::inAArch64 (ThreadContext *tc) |
| static OperatingMode | ArmISA::currOpMode (ThreadContext *tc) |
| static ExceptionLevel | ArmISA::currEL (ThreadContext *tc) |
| bool | ArmISA::ELIs64 (ThreadContext *tc, ExceptionLevel el) |
| bool | ArmISA::isBigEndian64 (ThreadContext *tc) |
| static uint8_t | ArmISA::itState (CPSR psr) |
| Addr | ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TTBCR tcr) |
| Removes the tag from tagged addresses if that mode is enabled. More... | |
| Addr | ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el) |
| static bool | ArmISA::inSecureState (SCR scr, CPSR cpsr) |
| bool | ArmISA::longDescFormatInUse (ThreadContext *tc) |
| bool | ArmISA::inSecureState (ThreadContext *tc) |
| uint32_t | ArmISA::getMPIDR (ArmSystem *arm_sys, ThreadContext *tc) |
| static uint32_t | ArmISA::mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2) |
| static void | ArmISA::mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2) |
| static uint32_t | ArmISA::mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1) |
| static uint32_t | ArmISA::msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt) |
| bool | ArmISA::mcrMrc15TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) |
| bool | ArmISA::mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) |
| bool | ArmISA::mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, HCR hcr, uint32_t iss) |
| bool | ArmISA::msrMrs64TrapToSup (const MiscRegIndex miscReg, ExceptionLevel el, CPACR cpacr) |
| bool | ArmISA::msrMrs64TrapToHyp (const MiscRegIndex miscReg, ExceptionLevel el, bool isRead, CPTR cptr, HCR hcr, bool *isVfpNeon) |
| bool | ArmISA::msrMrs64TrapToMon (const MiscRegIndex miscReg, CPTR cptr, ExceptionLevel el, bool *isVfpNeon) |
| bool | ArmISA::SPAlignmentCheckEnabled (ThreadContext *tc) |
| uint64_t | ArmISA::getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp) |
| void | ArmISA::skipFunction (ThreadContext *tc) |
| void | ArmISA::advancePC (PCState &pc, const StaticInstPtr &inst) |
| Addr | ArmISA::truncPage (Addr addr) |
| Addr | ArmISA::roundPage (Addr addr) |
| uint64_t | ArmISA::getExecutingAsid (ThreadContext *tc) |
| bool | ArmISA::decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int ®Idx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) |
| static int | ArmISA::decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r) |
| int | ArmISA::decodePhysAddrRange64 (uint8_t pa_enc) |
| Returns the n. More... | |
| uint8_t | ArmISA::encodePhysAddrRange64 (int pa_size) |
| Returns the encoding corresponding to the specified n. More... | |