37 #ifndef __DEV_NET_NS_GIGE_HH__
38 #define __DEV_NET_NS_GIGE_HH__
47 #include "params/NSGigE.hh"
392 #endif // __DEV_NET_NS_GIGE_HH__
void unserialize(CheckpointIn &cp) override
Unserialize an object.
EventWrapper< NSGigE,&NSGigE::cpuInterrupt > IntrEvent
const uint8_t EEPROM_READ
EventWrapper< NSGigE,&NSGigE::txKick > TxKickEvent
Addr rxFragPtr
ptr to the next byte in current fragment
void cpuIntrPost(Tick when)
Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy.
dp_regs regs
device register file
EEPROMState
EEPROM State Machine States.
bool cpuIntrPending() const
const uint8_t EEPROM_PMATCH2_ADDR
EventWrapper< NSGigE,&NSGigE::txDmaReadDone > txDmaReadEvent
TxState
Transmit State Machine states.
EEPROMState eepromState
EEPROM State Machine.
const uint16_t FHASH_SIZE
bool txHalt
halt the tx state machine after next packet
uint32_t rxDescCnt
count of bytes remaining in the current descriptor
NSGigEInt(const std::string &name, NSGigE *d)
Addr txFragPtr
ptr to the next byte in the current fragment
ns_desc32 txDesc32
DescCaches.
const uint8_t EEPROM_PMATCH0_ADDR
EventWrapper< NSGigE,&NSGigE::rxKick > RxKickEvent
Tick when() const
Get the time that the event is scheduled.
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
uint64_t Tick
Tick count type.
const uint8_t EEPROM_SIZE
const Params * params() const
void drainResume() override
Resume execution after a successful drain.
const uint8_t EEPROM_PMATCH1_ADDR
bool CTDD
Current Transmit Descriptor Done.
EventWrapper< NSGigE,&NSGigE::txDmaWriteDone > txDmaWriteEvent
std::shared_ptr< EthPacketData > EthPacketPtr
void transmit()
Retransmit event.
Ethernet device registers.
bool ioEnable
pci settings
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
EtherInt * getEthPort(const std::string &if_name, int idx) override
Additional function to return the Port of a memory object.
const uint16_t FHASH_ADDR
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
bool rxFilter(const EthPacketPtr &packet)
Base Ethernet Device declaration.
RxState
Receive State Machine States.
Ethernet device register definitions for the National Semiconductor DP83820 Ethernet controller...
bool rxHalt
halt the rx state machine after current packet
void serialize(CheckpointOut &cp) const override
Serialize an object.
EthPacketPtr txPacket
various helper vars
uint8_t filterHash[FHASH_SIZE]
for hash table memory.
Tick writeConfig(PacketPtr pkt) override
This is to write to the PCI general configuration registers.
EventWrapper< NSGigE,&NSGigE::rxDmaReadDone > rxDmaReadEvent
Tick read(PacketPtr pkt) override
This reads the device registers, which are detailed in the NS83820 spec sheet.
std::ostream CheckpointOut
EventWrapper< NSGigE,&NSGigE::txEventTransmit > TxEvent
const SimObjectParams * _params
Cached copy of the object parameters.
uint8_t perfectMatch[ETH_ADDR_LEN]
for perfect match memory.
uint32_t txDescCnt
count of bytes remaining in the current descriptor
const std::string & name() const
Return port name (for DPRINTF).
EventWrapper< NSGigE,&NSGigE::rxDmaWriteDone > rxDmaWriteEvent
void devIntrPost(uint32_t interrupts)
Interrupt management.
bool rxFilterEnable
receive address filter
RxState rxState
rx State Machine
NS DP83820 Ethernet device model.
bool CRDD
Current Receive Descriptor Done.
void devIntrClear(uint32_t interrupts)
void eepromKick()
Advance the EEPROM state machine Called on rising edge of EEPROM clock bit in MEAR.
virtual bool recvPacket(EthPacketPtr pkt)
uint32_t rxPktBytes
num of bytes in the current packet being drained from rxDataFifo
bool recvPacket(EthPacketPtr packet)