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arch
power
interrupts.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2011 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_POWER_INTERRUPT_HH__
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#define __ARCH_POWER_INTERRUPT_HH__
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#include "
base/misc.hh
"
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#include "params/PowerInterrupts.hh"
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#include "
sim/sim_object.hh
"
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class
BaseCPU
;
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class
ThreadContext
;
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namespace
PowerISA {
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class
Interrupts
:
public
SimObject
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{
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private
:
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BaseCPU
*
cpu
;
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public
:
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typedef
PowerInterruptsParams
Params
;
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const
Params
*
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params
()
const
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{
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return
dynamic_cast<
const
Params
*
>
(
_params
);
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}
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Interrupts
(
Params
*
p
) :
SimObject
(p),
cpu
(NULL)
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{}
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void
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setCPU
(
BaseCPU
* _cpu)
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{
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cpu
= _cpu;
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}
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void
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post
(
int
int_num,
int
index
)
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{
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panic
(
"Interrupts::post not implemented.\n"
);
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}
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void
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clear
(
int
int_num,
int
index
)
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{
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panic
(
"Interrupts::clear not implemented.\n"
);
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}
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void
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clearAll
()
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{
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panic
(
"Interrupts::clearAll not implemented.\n"
);
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}
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bool
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checkInterrupts
(
ThreadContext
*tc)
const
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{
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panic
(
"Interrupts::checkInterrupts not implemented.\n"
);
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}
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Fault
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getInterrupt
(
ThreadContext
*tc)
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{
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assert(
checkInterrupts
(tc));
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panic
(
"Interrupts::getInterrupt not implemented.\n"
);
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}
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void
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updateIntrInfo
(
ThreadContext
*tc)
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{
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panic
(
"Interrupts::updateIntrInfo not implemented.\n"
);
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}
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};
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}
// namespace PowerISA
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#endif // __ARCH_POWER_INTERRUPT_HH__
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MipsISA::index
Bitfield< 30, 0 > index
Definition:
pra_constants.hh:46
PowerISA::Interrupts::clear
void clear(int int_num, int index)
Definition:
interrupts.hh:73
panic
#define panic(...)
Definition:
misc.hh:153
PowerISA::Interrupts::checkInterrupts
bool checkInterrupts(ThreadContext *tc) const
Definition:
interrupts.hh:85
PowerISA::Interrupts::clearAll
void clearAll()
Definition:
interrupts.hh:79
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:93
misc.hh
PowerISA::Interrupts
Definition:
interrupts.hh:43
PowerISA::Interrupts::getInterrupt
Fault getInterrupt(ThreadContext *tc)
Definition:
interrupts.hh:91
PowerISA::Interrupts::Params
PowerInterruptsParams Params
Definition:
interrupts.hh:49
PowerISA::Interrupts::updateIntrInfo
void updateIntrInfo(ThreadContext *tc)
Definition:
interrupts.hh:98
PowerISA::Interrupts::params
const Params * params() const
Definition:
interrupts.hh:52
PowerISA::Interrupts::setCPU
void setCPU(BaseCPU *_cpu)
Definition:
interrupts.hh:61
sim_object.hh
PowerISA::Interrupts::cpu
BaseCPU * cpu
Definition:
interrupts.hh:46
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition:
sim_object.hh:107
PowerISA::Interrupts::post
void post(int int_num, int index)
Definition:
interrupts.hh:67
BaseCPU
Definition:
cpu_dummy.hh:45
PowerISA::Interrupts::Interrupts
Interrupts(Params *p)
Definition:
interrupts.hh:57
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:325
Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:184
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:94
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