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decoder.hh
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30 
31 #ifndef __ARCH_SPARC_DECODER_HH__
32 #define __ARCH_SPARC_DECODER_HH__
33 
35 #include "arch/sparc/registers.hh"
36 #include "arch/types.hh"
37 #include "cpu/static_inst.hh"
38 
39 namespace SparcISA
40 {
41 
42 class ISA;
43 class Decoder
44 {
45  protected:
46  // The extended machine instruction being generated
48  bool instDone;
50 
51  public:
52  Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
53  {}
54 
55  void process() {}
56 
57  void
59  {
60  instDone = false;
61  }
62 
63  // Use this to give data to the predecoder. This should be used
64  // when there is control flow.
65  void
66  moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
67  {
68  emi = inst;
69  // The I bit, bit 13, is used to figure out where the ASI
70  // should come from. Use that in the ExtMachInst. This is
71  // slightly redundant, but it removes the need to put a condition
72  // into all the execute functions
73  if (inst & (1 << 13)) {
74  emi |= (static_cast<ExtMachInst>(
75  asi << (sizeof(MachInst) * 8)));
76  } else {
77  emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
78  << (sizeof(MachInst) * 8));
79  }
80  instDone = true;
81  }
82 
83  bool
85  {
86  return true;
87  }
88 
89  bool
91  {
92  return instDone;
93  }
94 
95  void
97  {
98  asi = _asi;
99  }
100 
101  void takeOverFrom(Decoder *old) {}
102 
103  protected:
106 
107  public:
109 
115  {
116  return defaultCache.decode(this, mach_inst, addr);
117  }
118 
121  {
122  if (!instDone)
123  return NULL;
124  instDone = false;
125  return decode(emi, nextPC.instAddr());
126  }
127 };
128 
129 } // namespace SparcISA
130 
131 #endif // __ARCH_SPARC_DECODER_HH__
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:105
bool needMoreBytes()
Definition: decoder.hh:84
uint32_t MachInst
Definition: types.hh:41
ip6_addr_t addr
Definition: inet.hh:335
void setContext(MiscReg _asi)
Definition: decoder.hh:96
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:60
StaticInstPtr decode(SparcISA::PCState &nextPC)
Definition: decoder.hh:120
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:52
void process()
Definition: decoder.hh:55
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:42
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ExtMachInst emi
Definition: decoder.hh:47
uint64_t MiscReg
Definition: registers.hh:48
void takeOverFrom(Decoder *old)
Definition: decoder.hh:101
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition: decoder.hh:66
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:114
StaticInstPtr decodeInst(ExtMachInst mach_inst)
IntReg pc
Definition: remote_gdb.hh:91
uint64_t ExtMachInst
Definition: types.hh:42
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it...
Definition: bitfield.hh:67
bool instReady()
Definition: decoder.hh:90

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