Stefanos Kaxiras

Assistant Professor, University of Patras
Department of Electrical and Computer Engineering

(Formerly at Bell Labs, Lucent Technologies & Agere Systems)

For email please use: kaxiras ece upatras gr

or: kaxiras cs wisc edu

Book:
Computer Architecture Techniques for Power-Efficiency

Stefanos Kaxiras and Margaret Martonosi

Synthesis Lectures on Computer Architecture

Research Interests & Contributions: Memory Systems (Highly-Scalable Cache Coherence, Cache Management using Reuse Distances), Power (Decay), Instruction-based prediction, Network processors (IPStash IP-Lookup memories), Memory/Processor Integration (Datascalar/Distributed Vector Architectures)

• Managing Shared Caches with Reuse Distances and Decay (image: The Persistence of Memory, Dali)

  Modeling Cache Sharing on Chip Multiprocessor Architectures
  Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
  IISWC 2006.

  STATSHARE: A Statistical Model for Managing Cache Sharing via Decay (pdf 2.5MB!)
  Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
  MoBS 2006 with ISCA 33.

  Dynamic Dictionary-Based Data Compression for Level-1 Caches
  Georgios Keramidas, Konstantinos Aisopos, Stefanos Kaxiras
  ARCS 2006.

• HEAT!

  A Simple Mechanism to Adapt Leakage-Control Policies to Temperature
  Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas
  ISLPED 2005.

  4T-Decay Sensors: A New Class of Small, Fast, Robust,
  and Low-Power, Temperature/Leakage Sensors
  Stefanos Kaxiras, Polychronis Xekalakis
  ISLPED 2004.

• Network Processing

  IPSTASH-2:

  IPStash: A Set-Associative Memory Approach for Efficient IP-lookup
  Stefanos Kaxiras, Georgios Keramidas
  INFOCOM 2005.

  IPStash: a Power-Efficient Memory Architecture for IP-lookup (pdf)
  Stefanos Kaxiras, Georgios Keramidas
  IEEE MICRO-36.

  
  

• Timekeeping in the Memory System

  TCP: TAG Correlating Prefetchers (pdf)
  Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras,
  HPCA-9, Feb. 2003.

  Timekeeping Techniques for Predicting and Optimizing Memory Behavior
  Zhigang Hu, Stefanos Kaxiras and Margaret Martonosi
  IEEE International Solid-State Circuits Conference 2002
  

  Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior (pdf)
  Zhigang Hu, Stefanos Kaxiras and Margaret Martonosi
  29th International Symposium on Computer Architecture (ISCA-29), May 2002
  
  
  

• Leakage Power and Cache Decay (CERN image: Pion-Muon Decay)

  Implementing Decay Techniques using 4T Quasi-Static Memory Cells (pdf)
  P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi, D. W. Clark.
  Computer Architecture Letters, Volume 1, Sep. 2002
  

  Managing Leakage for Transient Data: Decay and Quasi-Static 4T Memory Cell (pdf)
  Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi and Douglas W. Clark
  International Symposium on Low Power Electronics and Design (ISLPED 2002), August 2002
  

  Let Caches Decay: Reducing Leakage Energy via Exploitation of Cache Generational Behavior (pdf)
  Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
  ACM Transactions on Computer Systems, May 2002
  

  Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power (pdf) (ps)
  Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
  ISCA 2001
  This paper also includes Adaptive Decay techniques and
  Instruction-based profiling for leakage control.

  Cache Decay: A Mechanism to Reduce Cache Leakage Power (pdf) (ps)
  Stefanos Kaxiras, Zhigang Hu, Girija Narlikar, Rae McLellan
  Power Aware Computer Systems Workshop with ASPLOS IX, 2000

• Low Power Caches/DSPs

  Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads (pdf) (ps)
  Stefanos Kaxiras, Girija Narlikar, Alan D. Berenbaum, Zhigang Hu
  International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2001

  Improving Cache Power Efficiency with an Asymmetric Set-Associative Cache (pdf) (ps)
  Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
  Workshop on Memory Performance Issues, 2001.
  Updated and expanded journal version (pdf)
  

  Simultaneous Multithreaded DSPs: Scaling from High performance to Low Power (pdf) (ps)
  Stefanos Kaxiras, Alan D. Berenbaum, Girija Narlikar
  Bell Laboratories Technical Memorandum 10009639-001024-06TM

• Instruction-based Prediction for Shared-memory

  Coherence Communication Prediction in Shared Memory Multiprocessors (pdf) (ps)
  Stefanos Kaxiras and Cliff Young
  HPCA-6, Jan. 2000
  

  Improving CC-NUMA Performance Using Instruction-Based Prediction (pdf) (ps)
  Stefanos Kaxiras and James R. Goodman.
  HPCA-5, Jan 1999.

  The Use of Instruction-based Prediction in Hardware Shared-Memory (pdf) (ps)
  Stefanos Kaxiras
  University of Wisconsin Computer Sciences Dept. TR-1368, April 1998
  

  Dynamic Optimizations in Linda Systems (pdf)
  An unpublished paper on prediction and Linda
  Stefanos Kaxiras & Ioannis Schoinas, 1993

  For more on instruction-based prediction see also my thesis below

  
  

• DIstributed Vector Architecture (DIVA)

  Distributed Vector Architectures (pdf) (ps)
  Stefanos Kaxiras
  Journal of Systems Architecture, 46 (2000) pp. 973-990.
  

  Distributed Vector Architecture: Beyond a Single Vector-IRAM (pdf) (ps)
  Stefanos Kaxiras, Rabin Sugumar, Jim Schwarzmeier
  Workshop on Mixing Logic and DRAM: Chipdf that Compute and Remember, Denver, Colorado, June 1, 1997
  

  Distributed Vector Architecture: Fine Grain Parallelism with Efficient Communication (pdf) (ps)
  Stefanos Kaxiras and Rabin Sugumar.
  University of Wisconsin Computer Sciences Dept. TR-1339, February 1997
  Also available from CRAY Research

• DataScalar Architecture (Galileo)

  DataScalar: Memory-Centric Approach to Computing (pdf) (ps)
  Stefanos Kaxiras, Doug Burger, James R. Goodman
  Journal of Systems Architecture, Special Issue on Microprocessor Architecture, No. 45 (1999) pp. 1001-1022.

  DataScalar Architectures (pdf) (ps)
  Doug Burger, Stefanos Kaxiras, and James R. Goodman
  24th International Symposium on Computer Architecture (ISCA), June, 1997.

  DataScalar Architectures and the SPSD Execution Model (pdf) (ps)
  Douglas Burger, Stefanos Kaxiras, and James R. Goodman
  University of Wisconsin Computer Sciences Dept. TR-1317, June 1996
  

• Highly-Scalable Cache Coherence
  This set of papers describes the GLOW extensions for cache coherence protocols (SCI or DIRiX protocols). GLOW allows these protocols to scale to 100's or 1000's of nodes. GLOW is a sophisticated solution that applies the basic CC protocol recursively, captures "georgaphical" locality, and is network independent.
  See my also my thesis (below) and SCI (SCI)

  IEEE 1596.2: Get the latest IEEE proposed Standard 1596.2
  IEEE Standard for Cache Optimization for Large Numbers of Processors using the Scalable Coherent Interface: DRAFT 0.36 (pdf) (ps)

  A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-Memory Multiprocessors (pdf) (ps)
  Stefanos Kaxiras, Stein Gjessing, and James R. Goodman.
  International Conference on Supercomputing, July 1998.

  Improving Request-Combining for Widely Shared Data in Shared-Memory Multiprocessors (pdf) (ps)
  Stefanos Kaxiras and James R. Goodman.
  Euromicro MPCS, April 1998.

  The GLOW Cache Coherence Protocol Extensions for Widely Shared Data (pdf) (ps)
  Stefanos Kaxiras and James R. Goodman
  Proceedings International Conference on Supercomputing, May 1996
  (Extended version as technical report TR-1305)
  

  Kiloprocessor Extensions to SCI (pdf) (ps)
  Stefanos Kaxiras
  Proceedings of the 10th International Parallel Processing Symposium, April 1996
  

  
  

• Thesis:

  Identification and Optimization of Sharing Patterns for Scalable Shared-Memory Multiprocessors

  (single sided pdf)
  (double sided pdf)
  Advisor: Jim Goodman

  
  

• Other

  PSM: Software Tool for Simulating, Prototyping, and Monitoring of Multiprocessor Systems,
  A. Stafylopatis, I. Papakonstantinou, S. Kaxiras
  Information and Software Technology 34, May 1992, pp. 313-325
  

  A Hardware Synthesis Methodology Using Prolog,
  P. Tsanakas, G. Papakonstantinou, S. Kaxiras
  Microprocessing and Microprogramming 32 (1991) 307-314, North-Holland