For Efthimios Kaxiras' page click here

Stefanos Kaxiras

Professor, Uppsala University, Sweden

(Formerly: Assistant Professor, University of Patras
Member of Technical Staff, Bell Labs, Lucent Technologies & Agere Systems)

For email please use: stefanos kaxiras it uu se

(just add at and dots to get address)

Computer Architecture Techniques for Power-Efficiency

Stefanos Kaxiras and Margaret Martonosi

Synthesis Lectures on Computer Architecture

* Mark D. Hill Series Editor
* Paperback: 220 pages
* Publisher: Morgan and Claypool Publishers; 1 edition (June 13, 2008)
* ISBN-10: 1598292080 ISBN-13: 978-1598292084
Morgan&Claypool book site

Decoupled Access Execute for Power Efficiency

Konstantinos Koukos, David Black-Schaffer, Vasileios Spiliopoulos, Stefanos Kaxiras, "Towards More Efficient Execution: A Decoupled Access-Execute Approach," ICS 2013

The end of Dennard scaling is expected to shrink the range of DVFS in future nodes, limiting the energy savings of this technique. This paper evaluates how much we can increase the effectiveness of DVFS by using a software decoupled access-execute approach. Decoupling the data access from execution allows us to apply optimal voltage-frequency selection for each phase and therefore improve energy efficiency over standard coupled execution.

The VIPS class of highly-efficient coherence protocols

We are releasing the first two papers on a new class of very simple, practically costless, invalidation-less, directory-less, snoop-less, coherence protocols. Please stay tuned for more information.

Virtual-cache coherence: Stefanos Kaxiras and Alberto Ros, "A New Perspective for Efficient Virtual-Cache Coherence" ISCA 2013

Directory-less NoC coherence: Alberto Ros, Stefanos Kaxiras, "Complexity-Effective Multicore Coherence" Parallel Architectures and Compilation Techniques (PACT) 2012

Snoop-less bus coherence: Stefanos Kaxiras, Alberto Ros "Efficient, Snoopless, System-On-Chip Coherence" IEEE System on Chip Conference (SOCC) 2012

Research Interests & Contributions: Memory Systems (Highly-Scalable Cache Coherence, Cache Management using Reuse Distances), Power (Decay), Instruction-based prediction, Network processors (IPStash IP-Lookup memories), Memory/Processor Integration (Datascalar/Distributed Vector Architectures)